#include "bcm283x.dtsi"
#include "bcm2835-common.dtsi"

/ {
	compatible = "brcm,bcm2837";

	soc {
		ranges = <0x7e000000 0x3f000000 0x1000000>,
			 <0x40000000 0x40000000 0x00001000>;
		dma-ranges = <0xc0000000 0x00000000 0x3f000000>;

		local_intc: local_intc@40000000 {
			compatible = "brcm,bcm2836-l1-intc";
			reg = <0x40000000 0x100>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&local_intc>;
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupt-parent = <&local_intc>;
		interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupt-parent = <&local_intc>;
		interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
			     <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
			     <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI
			     <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI
		always-on;
	};

	cpus: cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit

		/* Source for d/i-cache-line-size and d/i-cache-sets
		 * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system
		 * /about-the-l1-memory-system?lang=en
		 *
		 * Source for d/i-cache-size
		 * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks
		 */
		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x000000d8>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
			next-level-cache = <&l2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <1>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x000000e0>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
			next-level-cache = <&l2>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <2>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x000000e8>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
			next-level-cache = <&l2>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <3>;
			enable-method = "spin-table";
			cpu-release-addr = <0x0 0x000000f0>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
			next-level-cache = <&l2>;
		};

		/* Source for cache-line-size + cache-sets
		 * https://developer.arm.com/documentation/ddi0500
		 * /e/level-2-memory-system/about-the-l2-memory-system?lang=en
		 * Source for cache-size
		 * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf
		 */
		l2: l2-cache0 {
			compatible = "cache";
			cache-unified;
			cache-size = <0x80000>;
			cache-line-size = <64>;
			cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
			cache-level = <2>;
		};
	};
};

/* Make the BCM2835-style global interrupt controller be a child of the
 * CPU-local interrupt controller.
 */
&intc {
	compatible = "brcm,bcm2836-armctrl-ic";
	reg = <0x7e00b200 0x200>;
	interrupt-parent = <&local_intc>;
	interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
};

&cpu_thermal {
	coefficients = <(-538)	412000>;
};

/* enable thermal sensor with the correct compatible property set */
&thermal {
	compatible = "brcm,bcm2837-thermal";
	status = "okay";
};
