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[@`h"R`rc*# [B0[ck!RACaIc>@qT?B7qT;@R;I@RF߈߈w߈߈߈b߈s߈Sȵ߈߈9߈c߈߈9߈s߈s߈c߈c߈߈   !!!!!\!!!\\\\\\\!\\\\\\\\\\\\!!!!?#{ {#_stream-match-mask&smmu_domain->init_mutexdisabling translation TLB sync timed out -- SMMU may be deadlocked stream ID 0x%x out of range for SMMU (0x%x) SMR mask 0x%x out of range for SMMU (0x%x) Blocked unknown Stream ID 0x%hx; boot with "arm-smmu.disable_bypass=0" to allow, but this may have security implications Unexpected global fault, this could be serious GFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x iova to phys timed out on %pad. Falling back to software table walk. translation fault! PAR = 0x%llx Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d non-sfailed to allocate arm_smmu_device #global-interruptsmissing #global-interrupts property mmu-mastersSMMU5arm-smmu: deprecated "mmu-masters" DT property in use; %s support unavailable not probing due to mismatched DT properties found %d interrupts but expected at least %d failed to allocate %d irqs failed to get clocks %d SMMUv%d with: stage 1 translation stage 2 translation nested translation no translation support! address translation ops %scoherent table walk (IDR0.CTTW overridden by FW configuration) stream-matching supported, but no SMRs present! stream matching with %u register groups&smmu->stream_map_mutexSMMU address space size (0x%x) differs from mapped region size (0x%x)! impossible number of S2 context banks! %u context banks (%u stage-2 only) Supported page sizes: 0x%08lx Stage-1: %lu-bit VA -> %lu-bit IPA Stage-2: %lu-bit IPA -> %lu-bit PA found only %d context irq(s) but %d required smmu.%paarm-smmu global faultfailed to request global IRQ %d (%u) Failed to register iommu in sysfs Failed to register iommu preserved %d boot mapping%s failed to set DMA mask for table walker probing hardware configuration... cannot attach to SMMU, is it on the same bus? arm-smmu-context-faultfailed to request context IRQ %d (%u) arm-smmu?#{ {#___arm_smmu_tlb_syncarm_smmu_global_faultarm_smmu_context_fault $(*,arm,smmu-v1arm,smmu-v2arm,mmu-400arm,mmu-401arm,mmu-500cavium,smmu-v2nvidia,smmu-500qcom,smmu-v2arm_smmu.disable_bypassarm_smmu.force_stagearm_smmu.license=GPL v2arm_smmu.file=drivers/iommu/arm/arm-smmu/arm_smmuarm_smmu.alias=platform:arm-smmuarm_smmu.author=Will Deacon arm_smmu.description=IOMMU API for ARM architected SMMU implementationsarm_smmu.parm=disable_bypass:Disable bypass streams such that incoming transactions from devices that are not attached to an iommu domain will report an abort back to the device and will not be allowed to pass through the SMMU.arm_smmu.parmtype=disable_bypass:boolarm_smmu.parm=force_stage:Force SMMU mappings to be installed at a particular stage of translation. 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