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unsignedGP_3_9_DATAGP_1_2_FNFN_IP8_23_20avb0_mdio_pinsFN_MMC_D0FN_MMC_D1FN_MMC_D2FN_MMC_D3FN_MMC_D4FN_MMC_D5FN_MMC_D6FN_MMC_D7FN_VI0_CLKENBFN_VI0_DATA10FN_VI0_DATA11scif_clk_a_muxMMC_D1_MARKintc_ex_irq0_pinsGP_5_4_DATAscif4_data_pinsavb0_phy_int_muxIP3_3_0_MARKFSCLKST2_N_A_MARKGP_3_8_DATAGP_0_2_FNMSIOF1_SS1_MARKVI1_DATA7_MARKclass_spinlock_irq_tGP_2_15_FNtmu_tclk1_b_pinsFN_IP6_19_16FN_IP5_11_8pwm3_a_muxIP6_7_4_MARKSPEEDIN_B_MARKdu_clk_out_pinsMMC_D0_MARKFN_IP1_15_12FN_IP4_23_20hscif0_data_muxFN_VI1_DATA10FN_VI1_DATA11PWMFSW0_MARKscif3_ctrl_pinspwm3_groupsVI1_DATA6_MARKTASK_COMM_LENIP4_31_28_MARKFN_IP7_27_24FN_CTS4_NFN_IP4_11_8GP_1_0_FNSPEEDIN_A_MARKFN_IP1_3_0GP_0_18_FNFN_RX0qspi0_ctrl_muxFN_RX3FN_RX4TX0_MARKPIDTYPE_PIDGP_5_9_DATAFXR_TXDB_MARKVI1_DATA5_MARKmsiof2_groupsCTS0_N_MARKA4_MARKFN_D10FN_D11FN_D12FN_D13FN_D14FN_D15TDSELCTRLtmu_tclk2_b_muxMMC_D6_MARKFN_IP3_11_8GP_0_0_FNIP1_11_8_MARKhscif3_data_pinsFN_IP3_7_4GP_2_13_FNFN_MSIOF3_RXDcanfd1_data_pinsGP_5_8_DATAFN_RX1_AFN_RX1_BA3_MARKQSPI0_IO2_MARKFN_SEL_RFSO_0PWM0_A_MARKGP_0_15_DATARSEQ_CS_FLAG_NO_RESTART_ON_SIGNAL_BITPIN_EXTALRFN_MSIOF3_SS1FN_MSIOF3_SS2hscif3_ctrl_muxPINMUX_DATA_ENDGP_1_15_DATACTS1_N_MARKtmu_groupsGP_2_15_DATAGP_5_14_FNGP_3_15_DATApinmux_config_regsscif4_ctrl_muxGP_0_16_FNA2_MARKscif1_groupsavb0_link_pinsFN_VI0_DATA4FN_VI0_DATA5FN_VI0_DATA6FN_VI0_DATA7GP_0_14_DATAFN_VI0_DATA8FN_VI0_DATA9IP7_3_0_MARKintc_ex_irq3_muxGP_1_14_DATAGP_1_27_FNMSIOF3_SS1_MARKGP_2_14_DATAAVB0_TX_CTL_MARKFN_AVB0_TD0FN_AVB0_TD1FN_AVB0_TD2FN_AVB0_TD3GP_3_14_DATAFN_IP6_15_12GP_2_11_FNDU_DR7_MARKRXDB_EXTFXR_MARKPOCCTRL0SEL_I2C3_0_MARKPOCCTRL2IP1_31_28_MARKdu_oddf_muxFN_MSIOF2_SYNCGP_5_14_DATAFN_FSCLKST2_N_BFN_FSCLKST2_N_CD6_MARKGP_0_13_DATAGP_1_13_DATAIP8_27_24_MARKFN_SEL_RSP_0FN_SEL_RSP_1sh_pfc_pin_groupGP_2_13_DATACANFD0_RX_B_MARKavb0_groupsmsiof0_clk_pinsPIN_TDIpcpu_fcGP_3_13_DATAi2c2_muxFN_IP7_23_20DU_DR6_MARKPINMUX_MARK_BEGINFN_IP0_27_24DU_EXVSYNC_DU_VSYNC_MARKFN_MSIOF1_SYNCGP_5_13_DATAVI1_DATA11_MARKD5_MARKAVB0_RX_CTL_MARKGP_0_14_FNIP1_27_24_MARKMSIOF0_SCK_MARKWORK_STRUCT_INACTIVE_BITFN_IP0_7_4CTS3_N_MARKIP6_3_0_MARKvin0_clkenb_pinsGP_0_5_DATAvin1_clkenb_muxFN_MSIOF0_RXDmmc_ctrl_pinsmsiof3_txd_pinsDU_DR5_MARKGP_1_25_FNAVB0_TXCREFCLK_MARKA10_MARKFN_CLKOUTpwm0_groupsFN_MSIOF0_SYNCVI0_CLK_MARKIP0_23_20_MARKIP6_19_16_MARKAVB0_MDIO_MARKIRQ2_MARKFN_HRTS0_NFN_MSIOF0_SS1FN_MSIOF0_SS2FN_FSO_CFE_1_N_AFN_FSO_CFE_1_N_Bmsiof0_txd_muxFN_DU_CDEGP_0_4_DATAhscif3_data_muxmsiof1_txd_mux__int128IP1_19_16_MARKSCL1_MARKFN_DIGRF_CLKEN_OUTWORK_OFFQ_BH_BITQSPI0_SSL_MARKIP0_27_24_MARKA25_MARKmsiof3_txd_muxCTS4_N_MARKMM_SHMEMPAGESWORK_OFFQ_LEFTmsiof1_txd_pinsmsiof2_ss2_pinsmsiof1_ss1_muxscif0_clk_muxsh_pfc_soc_operationsFN_IP3_3_0vin1_sync_pinscanfd_clk_a_muxmsiof2_ss1_muxscif1_clk_muxGP_0_3_DATAscif3_groupsshort unsigned intsigned charCANFD_CLK_B_MARKA24_MARKscif3_clk_muxWORK_STRUCT_PENDING_BITscif4_clk_muxGP_1_4_DATAGP_1_23_FNFN_QSPI0_IO3msiof2_ss1_pinspocctrlintc_ex_irq4_muxMSIOF3_SYNC_MARKFN_HCTS0_NPWM4_A_MARKpwm1_a_muxIP6_23_20_MARKhscif2_groupsGP_0_2_DATAmsiof0_ss1_pinsFN_SCIF_CLK_AFN_SCIF_CLK_BFN_QSPI0_SPCLKSCL3_A_MARKIP6_11_8_MARKFN_IP3_31_28avb0_avtp_pps_pinsFN_SEL_SCIF1_0FN_SEL_SCIF1_1PINMUX_RESERVEDFN_IP2_19_16GP_1_3_DATAscif4_groupsFN_AVB0_PHY_INTFN_FSO_TOE_N_AFN_FSO_TOE_N_Bscif1_data_a_muxFN_IP5_27_24FN_IP0_23_20GP_2_4_DATASEL_PWM0_0_MARK__u16FSO_TOE_N_B_MARKcanfd_clk_b_muxrpc_data_muxIP6_15_12_MARKscif_clk_a_pinsFN_RTS0_NGP_0_10_FNGP_1_2_DATAIP6_31_28_MARKMSIOF2_SS2_MARKVI1_VSYNC_N_MARKFN_MSIOF1_SCKPCPU_FC_NRD14_MARKFN_VI0_DATA0FN_VI0_DATA1FN_VI0_DATA2FN_VI0_DATA3FN_QSPI0_IO2FN_DU_DB3FN_DU_DB4FN_DU_DB5FN_DU_DB6FN_DU_DB7FN_SCL3_AGP_1_21_FNGP_2_3_DATAFN_HTX2FN_HTX3FSO_TOE_N_A_MARKvin1_clk_muxFN_A9pinmux_bias_regsGP_5_9_FNFN_QSPI0_SSLWORK_OFFQ_FLAG_BITShscif1_ctrl_pinsmsiof1_clk_muxMSIOF2_SS1_MARKPINMUX_FUNCTION_BEGINFN_SDA3_AFN_SDA3_BSEL_PWM1_0_MARKFN_CANFD0_TX_AFN_CANFD0_TX_BTCLK1_A_MARKavb0_rgmii_pinsIP7_7_4_MARKGP_1_13_FNGP_2_2_DATAIP3_31_28_MARKFN_AVB0_TX_CTLGP_1_19_FNCANFD_CLK_A_MARK__u32GP_5_12_FNIP5_27_24_MARKpwm4_groupsMMC_CLK_MARKGP_3_3_DATAintc_ex_irq1_muxmsiof0_ss2_pinsRPC_INT_N_MARKlong intscif4_clk_pinsrpc_reset_pinsFN_HRTS1_Nmsiof3_sync_pinsFN_AVB0_RXCGP_3_2_DATAMSIOF0_RXD_MARKGP_5_7_FNFN_IP3_15_12GP_3_15_FNFXR_TXDA_MARKFN_TX0pwm4_a_muxFN_TX3GP_4_3_DATAGP_0_12_FNGP_1_22_FNhscif0_groupsFN_CANFD0_RX_AFN_CANFD0_RX_BFN_IP2_15_12scif3_data_muxcanfd0_data_b_muxFN_IP5_23_20GP_3_1_DATAFN_SEL_I2C3_0QSPI1_IO2_MARKSEL_TMU_1_MARKDU_DB7_MARKVI1_DATA0_MARKGP_5_10_FNFN_IP8_27_24GP_4_2_DATAAVB0_RD3_MARKCLKOUT_MARKFN_MSIOF3_TXDFN_PWM0_AFN_PWM0_BGP_1_18_FNFN_SEL_CANFD0_1sh_pfc_soc_infoFN_HCTS1_Navb0_avtp_match_pinsIP5_11_8_MARKqspi1_groupsVI0_DATA6_MARKGP_5_3_DATAHSCK3_MARKDU_DB6_MARKdu_cde_muxIP3_23_20_MARKSCK4_MARKvin1_field_muxGP_4_1_DATAAVB0_RD2_MARKGP_5_5_FNGP_3_13_FNPIN_TMSlong unsigned intVI1_CLKENB_MARKFN_DU_DG0FN_DU_DG1FN_DU_DG2FN_DU_DG3FN_DU_DG4FN_DU_DG5FN_DU_DG6FN_DU_DG7GNU C11 13.2.0 -mlittle-endian -mgeneral-regs-only -mabi=lp64 -mbranch-protection=pac-ret -mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=1288 -g -O2 -std=gnu11 -fshort-wchar -funsigned-char -fno-common -fno-PIE -fno-strict-aliasing -fno-asynchronous-unwind-tables -fno-unwind-tables -fno-delete-null-pointer-checks -fno-allow-store-data-races -fstack-protector-strong -fno-omit-frame-pointer -fno-optimize-sibling-calls -ftrivial-auto-var-init=zero -fno-stack-clash-protection -falign-functions=4 -fstrict-flex-arrays=3 -fno-strict-overflow -fstack-check=no -fconserve-stack -fno-var-tracking -femit-struct-debug-baseonly -fstack-protector-strongGP_5_2_DATAMSIOF1_SYNC_MARKavb0_txcrefclk_pinsDU_DB5_MARKIP8_19_16_MARKmsiof1_ss1_pinsmsiof1_rxd_pinsFN_RTS1_NFN_A0FN_A1FN_A2FN_A3FN_A4FN_A5FN_A6FN_A7FN_A8GP_1_25_DATACLK_EXTFXR_MARKFN_CANFD1_RXcanfd0_groupsVI0_DATA4_MARKGP_5_1_DATAcharGP_1_16_FNhscif0_data_pinsREAD_IMPLIES_EXECIP8_15_12_MARKFN_IP5_3_0MSIOF1_SCK_MARKdu_oddf_pinsAVB0_TD3_MARKSEL_SCIF1_1_MARKFN_VI1_CLKENBGP_1_24_DATAGP_5_3_FNhscif0_clk_pinsIP2_7_4_MARKA19_MARKDU_DR1_MARKGP_3_11_FNGP_3_8_FNqspi0_ctrl_pinsdu_sync_muxdu_sync_pinsFN_SEL_CANFD0_0FN_IP7_7_4D0_MARKcanfd1_groupsAVB0_TD2_MARKSEL_SCIF1_0_MARKCS1_N_MARKFN_IP8_3_0GP_1_23_DATAFN_MSIOF0_TXDSEL_RFSO_0_MARKPOCCTRL1SDA3_A_MARKQSPI1_SSL_MARKFN_SEL_TMU_0pinmux_bias_regA18_MARKDU_DR0_MARKFN_CANFD1_TXGP_2_8_FNIP0_31_28_MARKFN_IP1_27_24canfd1_data_muxSEL_RFSO_1_MARKFN_HRTS2_Nmsiof3_ss2_pinsscif_clk_b_muxFN_BS_Npwm2_groupsSEL_I2C3_1_MARKFN_HSCK3GP_1_14_FNDU_DG6_MARKGP_1_22_DATAHTX3_MARKD3_MARKDU_DB0_MARKFN_D0FN_D1FN_D2FN_D3FN_D4FN_D5FN_D6FN_D7FN_D8FN_D9FN_CS1_NSEL_PWM4_0_MARKRD_N_MARKFXR_TXENA_N_MARKPIDTYPE_SIDWORK_STRUCT_LINKED_BITpwm3_b_muxmsiof3_ss1_pinsGP_5_1_FNFN_SPEEDIN_AFN_SPEEDIN_BIP2_31_28_MARKDU_DG5_MARKGP_3_6_FNhscif1_clk_muxHTX2_MARKmsiof1_sync_pinsWORK_OFFQ_FLAG_SHIFThscif2_clk_muxavb0_link_muxvin0_clkenb_muxSEL_HSCIF0_0_MARKmsiof3_rxd_muxhscif3_clk_muxIP7_19_16_MARKFN_PWM1_AFN_PWM1_BSEL_RSP_1_MARKFN_HCTS2_NFN_IP2_3_0GP_2_6_FNr8a77970_pinmux_infoIRQ3_MARKrpc_data_pinsIP0_19_16_MARKAVB0_LINK_MARKGP_1_12_FNFN_TPU0TO0GP_4_4_FNFN_TPU0TO2FN_TPU0TO3SDA2_MARKavb0_phy_int_pinsMSIOF3_SS2_MARKFSO_CFE_0_N_A_MARKFN_IRQ0FN_IRQ1FN_AVB0_AVTP_MATCHFN_IRQ3FN_IRQ4FN_IRQ5FN_VI0_HSYNC_NFN_IP4_7_4FN_WE0_NFN_VI1_HSYNC_NFN_FXR_TXENA_Nvin0_data_pinspwm2_a_muxADDR_COMPAT_LAYOUTIP3_11_8_MARKGP_3_4_FNFN_RD_WR_NSDA1_MARKFN_QSPI1_SPCLKGP_1_9_FNdu_rgb666_pinsFN_IP4_31_28IP0_7_4_MARKFN_MMC_CLKFN_IP3_19_16intc_ex_irq5_pinsIP8_7_4_MARKD7_MARKvin0_field_muxIRQ1_MARKFN_IP6_27_24IP5_23_20_MARKcurrent_stack_pointerPIN_TCKFN_QSPI0_MOSI_IO0rpc_clk_pinsGP_2_4_FNFN_IP1_23_20FN_SEL_HSCIF0_1SDA0_MARKdu_rgb666_muxRX3_MARKGP_0_9_FNCANFD0_TX_A_MARKGP_LASTDIGRF_CLKIN_MARKMSIOF0_SYNC_MARKFN_MMC_CMDGP_1_10_FNGP_4_2_FNIP8_11_8_MARKFXR_CLKOUT2_MARKFN_IP1_31_28FN_SEL_TMU_1msiof1_ss2_pinsFN_VI1_DATA0FN_VI1_DATA1FN_VI1_DATA2FN_VI1_DATA3FN_VI1_DATA4FN_VI1_DATA5FN_VI1_DATA6FN_VI1_DATA7FN_VI1_DATA8FN_VI1_DATA9MMC_D4_MARKFN_VI0_CLKIP5_15_12_MARKFN_VI0_FIELDMSIOF1_RXD_MARKGP_3_2_FNtmu_tclk2_b_pinspinmux_ioctrl_regsrpc_groupsGP_1_7_FNPIN_DU_DOTCLKINFN_AVB0_MDCavb0_txcrefclk_muxFN_IP8_11_8rcar_pinmux_set_biasi2c4_groupsFN_HRTS3_NFN_AVB0_TXCSCL0_MARKFSCLKST2_N_C_MARKTX4_MARKGP_2_2_FNtmu_tclk2_a_pinsVI1_DATA9_MARKGP_0_7_FNFN_IP1_7_4FN_IP7_11_8GP_4_0_FNFN_MSIOF1_RXDPINMUX_MARK_ENDMMC_D2_MARKDU_EXODDF_DU_ODDF_DISP_CDE_MARKFSCLKST2_N_B_MARKTX3_MARKPCPU_FC_EMBEDIP4_27_24_MARKDU_EXHSYNC_DU_HSYNC_MARKpwm3_a_pinscanfd_clk_groupsVI1_DATA8_MARKFN_MSIOF1_SS1FN_MSIOF1_SS2RX4_MARKFN_IP6_11_8avb0_magic_muxGP_3_0_FNFN_PWM2_AFN_PWM2_Blong long unsigned intpid_typeMSIOF1_SS2_MARKGP_1_5_FNFN_DU_DR0FN_DU_DR1FN_DU_DR2FN_DU_DR3FN_DU_DR4FN_DU_DR5FN_DU_DR6FN_DU_DR7ADDR_LIMIT_32BITMSIOF1_TXD_MARKFN_IP6_23_20FN_IP7_31_28msiof1_ss2_muxA6_MARKmsiof2_rxd_pinsDU_DB1_MARKFDPIC_FUNCPTRSmsiof2_ss2_muxscif1_data_b_pinsGP_2_0_FNGP_0_18_DATAmsiof3_ss2_muxIP5_31_28_MARKmsiof2_clk_pinsmsiof0_sync_pinsGP_0_5_FNGP_1_18_DATAWORK_STRUCT_PWQ_SHIFTFN_FXR_TXENB_NFN_QSPI1_IO2FN_QSPI1_IO3intc_ex_irq5_muxVI0_DATA0_MARKA5_MARKFN_RTS3_Npwm1_b_muxFN_SEL_PWM1_1IP0_3_0_MARKMSIOF2_SCK_MARKscif4_ctrl_pinsGP_0_17_DATASEL_TMU_0_MARKIP8_3_0_MARKGP_1_17_DATAi2c0_muxi2c2_pinsmmc_ctrl_muxFN_QSPI1_MISO_IO1msiof1_clk_pinsclass_raw_spinlock_irqsave_tVI0_CLKENB_MARKA7_MARKDU_DISP_MARKIP3_7_4_MARKFN_RPC_RESET_NGP_1_3_FNscif1_data_b_muxQSPI0_IO3_MARKpinmux_pinsintc_ex_irq1_pinsPWM0_B_MARKD9_MARKGP_0_16_DATAVI1_CLK_MARKGP_1_16_DATAFN_DIGRF_CLKOUTi2c1_pinsmsiof0_sync_muxGP_2_16_DATAIP2_11_8_MARKGP_0_20_FNmsiof3_sync_muxGP_3_16_DATAIP2_23_20_MARKGP_0_3_FNSCK0_MARKGP_0_8_DATAFN_EX_WAIT0RTS0_N_MARKGP_2_16_FNIP7_27_24_MARKD8_MARKi2c0_pinsi2c2_groupsFN_QSPI1_SSLPWM1_B_MARKWORK_OFFQ_POOL_BITSlong long intFN_PWMFSW0A13_MARKhscif3_ctrl_pinsFN_MSIOF3_SYNCIP2_15_12_MARKWE1_N_MARKGP_1_1_FNhscif1_ctrl_muxFN_DU_EXHSYNC_DU_HSYNCavb0_avtp_pps_muxscif0_ctrl_pinsGP_0_19_FNPWM1_A_MARKGP_0_7_DATAFN_AVB0_MDIOPIN_VDDQ_AVB0FN_AVB0_AVTP_PPSFN_IP0_31_28STICKY_TIMEOUTShscif0_ctrl_muxSCL4_MARKvin1_clk_pinsA12_MARKFSO_CFE_1_N_B_MARKVI1_FIELD_MARKFN_RXDB_EXTFXRVI1_DATA1_MARKPWM2_B_MARKFN_IP2_27_24msiof0_rxd_pinsGP_0_1_FNFN_HTX0class_raw_spinlock_tFN_HTX1DU_DG0_MARKGP_2_14_FNMMC_D3_MARKGP_0_6_DATAvin0_clk_muxFN_PWM3_AFN_PWM3_BA11_MARKFSO_CFE_1_N_A_MARKMM_FILEPAGESscif3_clk_pinsPWM2_A_MARKGP_1_7_DATApwm4_b_muxIP6_27_24_MARKIP4_11_8_MARKFN_AVB0_LINKclass_spinlock_tMM_SWAPENTSFN_AVB0_TXCREFCLKPWM3_B_MARKpinmux_groupsvin1_clkenb_pinsGP_0_17_FNIP1_7_4_MARKFN_DIGRF_CLKEN_INGP_1_6_DATAPINMUX_FUNCTION_ENDvin0_groupsADDR_LIMIT_3GBSEL_PWM4_1_MARKFN_QSPI1_MOSI_IO0rpc_int_pinsFN_RTS4_Nsh_pfc_pinSEL_RSP_0_MARKPWM3_A_MARKscif3_data_pinsGP_2_7_DATAFN_SDA0FN_SDA1FN_SDA2FN_SDA4FN_SEL_RFSO_1GP_2_12_FNunsigned intQSPI0_SPCLK_MARKscif4_data_muxdu_disp_muxGP_1_5_DATAEX_WAIT0_MARKPWM4_B_MARKIP7_11_8_MARKmsiof0_txd_pinsintc_ex_irq3_pinsGP_5_7_DATAGP_2_6_DATAshort intSCL3_B_MARKFN_RD_NA8_MARKvin1_groupsMSIOF2_RXD_MARKFN_RPC_INT_NHRTS0_N_MARKFN_IP5_31_28GP_3_7_DATAGP_0_15_FNFN_IP4_19_16FN_SEL_PWM0_0FN_SEL_PWM0_1msiof0_groupsD12_MARKhscif2_clk_pinsGP_2_5_DATASEL_PWM0_1_MARKRSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE_BITRX1_A_MARKGP_1_26_FNFN_IP2_23_20scif_clk_b_pinsFN_DU_DB0FN_DU_DB1FN_DU_DB2FN_RXDA_EXTFXRFN_IP6_3_0GP_3_6_DATAGP_2_10_FNdrivers/pinctrl/renesas/pfc-r8a77970.c/kernel/work/linux-6.11/kernel/work/linux-6.11drivers/pinctrl/renesas./include/uapi/asm-generic./include/asm-generic./include/uapi/linux./include/linux./arch/arm64/include/asmpfc-r8a77970.cpfc-r8a77970.cint-ll64.hint-ll64.hpersonality.hmm_types_task.hspinlock.hprocessor.hpid_types.hrseq.hsched.hpercpu.hworkqueue.hmm_types.hstack_pointer.hsh_pfc.hGCC: (Ubuntu 13.2.0-23ubuntu4) 13.2.0GNU x ++.(?/ KxY`j(}h6 X( Dh D+ @H U` j <0    0F\ r00H 0 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+(=pfc-r8a77970.c$xr8a77970_pin_to_pocctrl$dr8a77970_pfc_opspinmux_pinspinmux_groupspinmux_functionspinmux_config_regspinmux_bias_regspinmux_ioctrl_regspinmux_data__compound_literal.1__compound_literal.0__compound_literal.3__compound_literal.5__compound_literal.4__compound_literal.7__compound_literal.6__compound_literal.9__compound_literal.8__compound_literal.11__compound_literal.10__compound_literal.13__compound_literal.15__compound_literal.17__compound_literal.19__compound_literal.21__compound_literal.23__compound_literal.25__compound_literal.27__compound_literal.29__compound_literal.28__compound_literal.31__compound_literal.30avb0_groupscanfd_clk_groupscanfd0_groupscanfd1_groupsdu_groupshscif0_groupshscif1_groupshscif2_groupshscif3_groupsi2c0_groupsi2c1_groupsi2c2_groupsi2c3_groupsi2c4_groupsintc_ex_groupsmmc_groupsmsiof0_groupsmsiof1_groupsmsiof2_groupsmsiof3_groupspwm0_groupspwm1_groupspwm2_groupspwm3_groupspwm4_groupsqspi0_groupsqspi1_groupsrpc_groupsscif_clk_groupsscif4_groupstmu_groupsvin0_groupsvin1_groupsavb0_link_pinsavb0_link_muxavb0_magic_pinsavb0_magic_muxavb0_phy_int_pinsavb0_phy_int_muxavb0_mdio_pinsavb0_mdio_muxavb0_rgmii_pinsavb0_rgmii_muxavb0_txcrefclk_pinsavb0_txcrefclk_muxavb0_avtp_pps_pinsavb0_avtp_pps_muxavb0_avtp_capture_pinsavb0_avtp_capture_muxavb0_avtp_match_pinsavb0_avtp_match_muxcanfd_clk_a_pinscanfd_clk_a_muxcanfd_clk_b_pinscanfd_clk_b_muxcanfd0_data_a_pinscanfd0_data_a_muxcanfd0_data_b_pinscanfd0_data_b_muxcanfd1_data_pinscanfd1_data_muxdu_rgb666_pinsdu_rgb666_muxdu_clk_out_pinsdu_clk_out_muxdu_sync_pinsdu_sync_muxdu_oddf_pinsdu_oddf_muxdu_cde_pinsdu_cde_muxdu_disp_pinsdu_disp_muxhscif0_data_pinshscif0_data_muxhscif0_clk_pinshscif0_clk_muxhscif0_ctrl_pinshscif0_ctrl_muxhscif1_data_pinshscif1_data_muxhscif1_clk_pinshscif1_clk_muxhscif1_ctrl_pinshscif1_ctrl_muxhscif2_data_pinshscif2_data_muxhscif2_clk_pinshscif2_clk_muxhscif2_ctrl_pinshscif2_ctrl_muxhscif3_data_pinshscif3_data_muxhscif3_clk_pinshscif3_clk_muxhscif3_ctrl_pinshscif3_ctrl_muxi2c0_pinsi2c0_muxi2c1_pinsi2c1_muxi2c2_pinsi2c2_muxi2c3_a_pinsi2c3_a_muxi2c3_b_pinsi2c3_b_muxi2c4_pinsi2c4_muxintc_ex_irq0_pinsintc_ex_irq0_muxintc_ex_irq1_pinsintc_ex_irq1_muxintc_ex_irq2_pinsintc_ex_irq2_muxintc_ex_irq3_pinsintc_ex_irq3_muxintc_ex_irq4_pinsintc_ex_irq4_muxintc_ex_irq5_pinsintc_ex_irq5_muxmmc_data_pinsmmc_data_muxmmc_ctrl_pinsmmc_ctrl_muxmsiof0_clk_pinsmsiof0_clk_muxmsiof0_sync_pinsmsiof0_sync_muxmsiof0_ss1_pinsmsiof0_ss1_muxmsiof0_ss2_pinsmsiof0_ss2_muxmsiof0_txd_pinsmsiof0_txd_muxmsiof0_rxd_pinsmsiof0_rxd_muxmsiof1_clk_pinsmsiof1_clk_muxmsiof1_sync_pinsmsiof1_sync_muxmsiof1_ss1_pinsmsiof1_ss1_muxmsiof1_ss2_pinsmsiof1_ss2_muxmsiof1_txd_pinsmsiof1_txd_muxmsiof1_rxd_pinsmsiof1_rxd_muxmsiof2_clk_pinsmsiof2_clk_muxmsiof2_sync_pinsmsiof2_sync_muxmsiof2_ss1_pinsmsiof2_ss1_muxmsiof2_ss2_pinsmsiof2_ss2_muxmsiof2_txd_pinsmsiof2_txd_muxmsiof2_rxd_pinsmsiof2_rxd_muxmsiof3_clk_pinsmsiof3_clk_muxmsiof3_sync_pinsmsiof3_sync_muxmsiof3_ss1_pinsmsiof3_ss1_muxmsiof3_ss2_pinsmsiof3_ss2_muxmsiof3_txd_pinsmsiof3_txd_muxmsiof3_rxd_pinsmsiof3_rxd_muxpwm0_a_pinspwm0_a_muxpwm0_b_pinspwm0_b_muxpwm1_a_pinspwm1_a_muxpwm1_b_pinspwm1_b_muxpwm2_a_pinspwm2_a_muxpwm2_b_pinspwm2_b_muxpwm3_a_pinspwm3_a_muxpwm3_b_pinspwm3_b_muxpwm4_a_pinspwm4_a_muxpwm4_b_pinspwm4_b_muxqspi0_ctrl_pinsqspi0_ctrl_muxrpc_data_pinsrpc_data_muxqspi1_ctrl_pinsqspi1_ctrl_muxrpc_clk_pinsrpc_clk_muxrpc_ctrl_pinsrpc_ctrl_muxrpc_reset_pinsrpc_reset_muxrpc_int_pinsrpc_int_muxrpc_wp_pinsrpc_wp_muxscif_clk_a_pinsscif_clk_a_muxscif_clk_b_pinsscif_clk_b_muxscif1_data_a_pinsscif1_data_a_muxscif1_data_b_pinsscif1_data_b_muxscif4_data_pinsscif4_data_muxscif4_clk_pinsscif4_clk_muxscif4_ctrl_pinsscif4_ctrl_muxtmu_tclk1_a_pinstmu_tclk1_a_muxtmu_tclk1_b_pinstmu_tclk1_b_muxtmu_tclk2_a_pinstmu_tclk2_a_muxtmu_tclk2_b_pinstmu_tclk2_b_muxvin0_data_pinsvin0_data_muxvin0_sync_pinsvin0_sync_muxvin0_field_pinsvin0_field_muxvin0_clkenb_pinsvin0_clkenb_muxvin0_clk_pinsvin0_clk_muxvin1_data_pinsvin1_data_muxvin1_sync_pinsvin1_sync_muxvin1_field_pinsvin1_field_muxvin1_clkenb_pinsvin1_clkenb_muxvin1_clk_pinsvin1_clk_muxr8a77970_pinmux_inforcar_pinmux_get_biasrcar_pinmux_set_bias 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