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int__kernel_size_tarmv8_pmuv3_perf_map__after_TPIDR_EL2kcsan_check_accessperf_sample_dataAPGAKEYLO_EL1write_pmuserenrPAR_EL1armv8_vulcan_perf_cache_mapwidthAMAIR_EL1AMAIR_EL2userpgl_yesarmv9_cortex_x4_pmu_initARMPMU_ATTR_GROUP_CAPS__kern_my_cpu_offset__after_ESR_EL1CPACR_EL1irqreturn_tformat_attr_rdpmcMPIDR_EL1armv8pmu_write_counteralternative_has_cap_likelykvm_clr_pmu_events__kernel_ssize_tclock_read_dataPERF_COUNT_SW_ALIGNMENT_FAULTSlockup_detector_retry_initarmv8_pmu_initPERF_COUNT_HW_CACHE_OP_WRITEoffsetPERF_COUNT_SW_PAGE_FAULTS_MINsizecpus_have_final_cap__after_FAR_EL1page__after_HSTR_EL2__this_cpu_preempt_checkarmv8_pmu_device_probePMCCNTR_EL0__u8ZCR_EL1ZCR_EL2__after_ELR_EL1__compiletime_assert_630__before_ESR_EL1boolPERF_SAMPLE_STACK_USERPERF_COUNT_HW_BRANCH_MISSESPERF_COUNT_HW_REF_CPU_CYCLESPERF_COUNT_SW_EMULATION_FAULTS__kernel_long_t__cpu_online_maskPERF_COUNT_HW_CACHE_MISSESPMUSERENR_EL0armv8pmu_event_has_user_read__mptrPERF_SAMPLE_IDENTIFIERAFSR1_EL1smp_cond_func_tarmv8_nvidia_denver_pmu_initword__before_FAR_EL1HSTR_EL2HFGITR_GROUPbitmap_from_arr32__before_PIRE0_EL1cpuid_feature_extract_unsigned_fieldPERF_SAMPLE_REGS_USERlenpinfoDISR_EL1APIAKEYHI_EL1dev_attr_bus_slots__NO_FGT_GROUP__is_kernel_in_hyp_modePIRE0_EL1armv8_pmu_of_device_idsPMCR_EL0TPIDR_EL0TPIDR_EL1TPIDR_EL2devicedev_get_drvdataof_device_idlong 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intarm_pmuirqreturnarmv8pmu_probe_pmuattributeTCR2_EL1armv8pmu_events_sysfs_showarmpmusysfs_emit__before_CPACR_EL1PERF_SAMPLE_ADDRth_comparearmv8pmu_enable_event_irqHPFAR_EL2PERF_SAMPLE_DATA_SRCthreshold_max_showarmv8pmu_handle_irqTPIDRRO_EL0armv8_neoverse_e1_pmu_initarmv8_neoverse_v2_pmu_initESR_EL1ESR_EL2armv8pmu_disable_eventPERF_TYPE_BREAKPOINTraw_atomic_long_fetch_orarmv8_a57_map_eventarmv8pmu_event_get_thresholdarmv8pmu_has_long_event__UNIQUE_ID_ddebug647__UNIQUE_ID_ddebug649threshold_count_showfeaturesarmv8_pmuv3_pmu_initCNTHCTL_EL2NR_KVM_EL0_TIMERSPERF_COUNT_HW_CACHE_NODE__after_AFSR1_EL1periodwrite_pmcntensetpmovsrarmv8pmu_set_event_filterkobjformat_attr_eventfieldproc_dointvec_minmaxsysctl_vals__before_TCR_EL1regs__before_CNTV_CVAL_EL0armv9_cortex_x3_pmu_initPERF_COUNT_HW_INSTRUCTIONS__int128__ll_sc__cmpxchg_case_8umode_tELR_EL1ELR_EL2__VNCR_START__static_key_false__before_AFSR0_EL1__before_CONTEXTIDR_EL1__irq_regsPERF_COUNT_HW_BRANCH_INSTRUCTIONSTFSRE0_EL1CNTHP_CVAL_EL2armv8pmu_disable_event_irqwrite_pmccfiltrPERF_COUNT_HW_MAXraw_atomic_long_andnotkvm_arch_timersrdpmc_showperf_hw_idarch_perf_update_userpagectl_tablenamePERF_SAMPLE_TIMEAFSR0_EL1AFSR0_EL2__before_TPIDR_EL2VTTBR_EL2__before_VTCR_EL2__after_VMPIDR_EL2bus_width__s64armv8_pmuv3_perf_cache_mapPERF_COUNT_HW_CACHE_MAXRGSR_EL1__compiletime_assert_106__compiletime_assert_107armv8pmu_write_evtypeshort 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