h8 ( Tradxa,rock-5arockchip,rk3588s +7Radxa ROCK 5 Model Aopp-table-cluster0operating-points-v2=H opp-408000000PQW q q~ q q~e@vopp-600000000P#FW q q~ q q~e@opp-816000000P0,W q q~ q q~e@opp-1008000000P<W q q~ q q~e@opp-1200000000PGW X X~ X X~e@opp-1416000000PTfrW ~ ~e@opp-1608000000P_"W Y Y~ Y Y~e@opp-1800000000PkIW~~~~~~e@opp-table-cluster1operating-points-v2=  H LkIHopp-408000000PQW ' 'B@ L LB@e@vopp-600000000P#FW ' 'B@ L LB@e@opp-816000000P0,W ' 'B@ L LB@e@opp-1008000000P<W h hB@ L LB@e@opp-1200000000PGW  B@ L LB@e@opp-1416000000PTfrW L LB@ L LB@e@opp-1608000000P_"W ` `B@ ` `B@e@opp-1800000000PkIW X XB@ X XB@e@opp-2016000000Px)W P PB@ P PB@e@opp-2208000000PhWHHB@HHB@e@opp-table-cluster2operating-points-v2=  H LkIHopp-408000000PQW ' 'B@ L LB@e@vopp-600000000P#FW ' 'B@ L LB@e@opp-816000000P0,W ' 'B@ L LB@e@opp-1008000000P<W h hB@ L LB@e@opp-1200000000PGW  B@ L LB@e@opp-1416000000PTfrW L LB@ L LB@e@opp-1608000000P_"W ` `B@ ` `B@e@opp-1800000000PkIW X XB@ X XB@e@opp-2016000000Px)W P PB@ P PB@e@opp-2208000000PhWHHB@HHB@e@cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1 cluster2core0 core1 cpu@0cpuarm,cortex-a55psci  0,# 7GT@fs@Hcpu@100cpuarm,cortex-a55psci # 7GT@fs@Hcpu@200cpuarm,cortex-a55psci # 7GT@fs@Hcpu@300cpuarm,cortex-a55psci # 7GT@fs@Hcpu@400cpuarm,cortex-a76psci  0,#7GT@fs@Hcpu@500cpuarm,cortex-a76psci #7GT@fs@H cpu@600cpuarm,cortex-a76psci  0,#7GT@fs@H cpu@700cpuarm,cortex-a76psci #7GT@fs@H idle-statespscicpu-sleeparm,idle-stated*x:Hl2-cache-l0cacheIV@hKWHl2-cache-l1cacheIV@hKWHl2-cache-l2cacheIV@hKWHl2-cache-l3cacheIV@hKWHl2-cache-b0cacheIV@hKWHl2-cache-b1cacheIV@hKWHl2-cache-b2cacheIV@hKWHl2-cache-b3cacheIV@hKWHl3-cachecacheI0V@hKWHfirmwareopteelinaro,optee-tzsmcscmi arm,scmi-smcep+protocol@14vH protocol@16pmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0smcclock-0 fixed-clock)׫spllvthermal-zonessoc-thermal4 tripstrip-point-0$passivetrip-point-1LpassiveH!trip-point-28 criticalcooling-mapsmap0!`  /bigcore0-thermal tripstrip-point-0$passivetrip-point-1LpassiveH"trip-point-28 criticalcooling-mapsmap0"  /bigcore1-thermal tripstrip-point-0$passivetrip-point-1LpassiveH#trip-point-28 criticalcooling-mapsmap0# /littlecore-thermal tripstrip-point-0$passivetrip-point-1LpassiveH$trip-point-28 criticalcooling-mapsmap0$0 /center-thermal tripstrip-point-0$passivetrip-point-1Lpassivetrip-point-28 criticalgpu-thermal tripstrip-point-0$passivetrip-point-1Lpassivetrip-point-28 criticalnpu-thermal tripstrip-point-0$passivetrip-point-1Lpassivetrip-point-28 criticaltimerarm,armv8-timerP    %?+power-domain@10 %!%#%"@power-domain@11 %!%#%"Apower-domain@12 %%%BCDEpower-domain@13 +power-domain@14(%%%%%Fpower-domain@15 %%%%Gpower-domain@16%% HIJ+power-domain@17 %%%% KLMpower-domain@21%%%%%%%%%%%%%%%%%% NOPQRSTU+power-domain@23%C%A%Vpower-domain@14 %%%%Fpower-domain@15%%%Gpower-domain@22%%Wpower-domain@24%[%Z%]XY+power-domain@258%%%%%%%ZZpower-domain@268%%%%%%%Q[\power-domain@270%%%%%%]^_`+power-domain@28 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H]qos@fdf40500rockchip,rk3588-qossyscon H^qos@fdf40600rockchip,rk3588-qossyscon H_qos@fdf40800rockchip,rk3588-qossyscon H`qos@fdf41000rockchip,rk3588-qossyscon Haqos@fdf41100rockchip,rk3588-qossyscon Hbqos@fdf60000rockchip,rk3588-qossyscon HHqos@fdf60200rockchip,rk3588-qossyscon HIqos@fdf60400rockchip,rk3588-qossyscon HJqos@fdf61000rockchip,rk3588-qossyscon HKqos@fdf61200rockchip,rk3588-qossyscon HLqos@fdf61400rockchip,rk3588-qossyscon HMqos@fdf62000rockchip,rk3588-qossyscon HFqos@fdf63000rockchip,rk3588-qossyscon0 HGqos@fdf64000rockchip,rk3588-qossyscon@ HVqos@fdf66000rockchip,rk3588-qossyscon` HNqos@fdf66200rockchip,rk3588-qossysconb HOqos@fdf66400rockchip,rk3588-qossyscond HPqos@fdf66600rockchip,rk3588-qossysconf HQqos@fdf66800rockchip,rk3588-qossysconh HRqos@fdf66a00rockchip,rk3588-qossysconj HSqos@fdf66c00rockchip,rk3588-qossysconl HTqos@fdf66e00rockchip,rk3588-qossysconn HUqos@fdf67000rockchip,rk3588-qossysconp HWqos@fdf67200rockchip,rk3588-qossysconr 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@disabledmmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc,@  %%Sbiuciuciu-driveciu-sampleрGdefaultU}~((@okay #/mmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc-@ %%%%Sbiuciuciu-driveciu-sample GdefaultU(% @disabledmmc@fe2e0000rockchip,rk3588-dwcmshc.%-%.%,  n6 (%,%*%+%-%.Scorebusaxiblocktimer UGdefault(%%%%%ycorebusaxiblocktimer@okay<BP_i2s@fe470000rockchip,rk3588-i2s-tdmG%+%/%(Smclk_txmclk_rxhclk%)%-%%V77[txrx(&%*%+ ytx-mrx-myGdefaultU@okayportHendpointi2sHi2s@fe480000rockchip,rk3588-i2s-tdmH%y%}%uSmclk_txmclk_rxhclkV77[txrx%^%_ ytx-mrx-myGdefault(U @disabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2sI%%Si2s_clki2s_hclk%%V[txrx(&yGdefaultU @disabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2sJ%%%Si2s_clki2s_hclk%"%V[txrx(&yGdefaultU @disabledinterrupt-controller@fe600000 arm,gic-v3 `h Ba8L+Hmsi-controller@fe640000arm,gic-v3-itsdHnmsi-controller@fe660000arm,gic-v3-itsfppi-partitionsinterrupt-partition-0Hinterrupt-partition-1 Hdma-controller@fea10000arm,pl330arm,primecell@ VW%n Sapb_pclk H7dma-controller@fea30000arm,pl330arm,primecell@ XY%o Sapb_pclk Hi2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2c%%{ Si2cpclk>UGdefault+ @disabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c%%| Si2cpclk?UGdefault+@okayregulator@42rockchip,rk8602B vdd_npu_s0dp~26regulator-state-mem=eeprom@50belling,bl24c16aatmel,24c16P i2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c%%} Si2cpclk@UGdefault+@okayi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c%%~ Si2cpclkAUGdefault+ @disabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c%% Si2cpclkBUGdefault+@okaytimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer !%T%W Spclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt%d%c Stclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiF%%Sspiclkapb_pclkV77[txrx  UGdefault+ @disabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiG%%Sspiclkapb_pclkV77[txrx  UGdefault+ @disabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiH%%Sspiclkapb_pclkV[txrx UGdefault+@okay% pmic@0rockchip,rk806 GdefaultU !B@ 36 ?6 K6 W6 c6 o6 {6 6 6 6  6   6  dvs1-null-pins gpio_pwrctrl2 pin_fun0Hdvs2-null-pins gpio_pwrctrl2 pin_fun0Hdvs3-null-pins gpio_pwrctrl3 pin_fun0Hregulatorsdcdc-reg1 vdd_gpu_s0dp~0 regulator-state-mem=dcdc-reg2vdd_cpu_lit_s0dp~0Hregulator-state-mem=dcdc-reg3 vdd_log_s0 L q0regulator-state-mem= 2 qdcdc-reg4 vdd_vdenc_s0dp~0regulator-state-mem=dcdc-reg5 vdd_ddr_s0 L 0regulator-state-mem= 2 Pdcdc-reg6 vdd2_ddr_s3regulator-state-mem Ndcdc-reg7vdd_2v0_pldo_s30Hregulator-state-mem N 2dcdc-reg8 vcc_3v3_s32Z2Zregulator-state-mem N 22Zdcdc-reg9 vddq_ddr_s0regulator-state-mem=dcdc-reg10 vcc_1v8_s3w@w@regulator-state-mem N 2w@pldo-reg1 avcc_1v8_s0w@w@Hregulator-state-mem=pldo-reg2 vcc_1v8_s0w@w@regulator-state-mem= 2w@pldo-reg3 avdd_1v2_s0OOregulator-state-mem=pldo-reg4 vcc_3v3_s02Z2Z0Hregulator-state-mem=pldo-reg5 vccio_sd_s0w@2Z0Hregulator-state-mem=pldo-reg6 pldo6_s3w@w@regulator-state-mem N 2w@nldo-reg1 vdd_0v75_s3 q qregulator-state-mem N 2 qnldo-reg2vdd_ddr_pll_s0 P Pregulator-state-mem= 2 Pnldo-reg3 avdd_0v75_s0 q qregulator-state-mem=nldo-reg4 vdd_0v85_s0 P Pregulator-state-mem=nldo-reg5 vdd_0v75_s0 q qregulator-state-mem=spi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiI%%Sspiclkapb_pclkV[txrx  UGdefault+ @disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartL%%Sbaudclkapb_pclkV77 [txrxUGdefaultoe @disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartM%%Sbaudclkapb_pclkV7 7 [txrxUGdefaultoe@okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartN%%Sbaudclkapb_pclkV7 7 [txrxUGdefaultoe @disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartO%%Sbaudclkapb_pclkV [txrxUGdefaultoe @disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartP%%Sbaudclkapb_pclkV [txrxUGdefaultoe @disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartQ%%Sbaudclkapb_pclkV [txrxUGdefaultoe @disabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartR%%Sbaudclkapb_pclkVll[txrxUGdefaultoe @disabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartS%%Sbaudclkapb_pclkVl l [txrxUGdefaultoe @disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartT%%Sbaudclkapb_pclkVl l [txrxUGdefaultoe @disabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm%L%K SpwmpclkUGdefault| @disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm%L%K SpwmpclkUGdefault| @disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm %L%K SpwmpclkUGdefault| @disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0%L%K SpwmpclkUGdefault| @disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm%O%N SpwmpclkUGdefault| @disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm%O%N SpwmpclkUGdefault| @disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm %O%N SpwmpclkUGdefault| @disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0%O%N SpwmpclkUGdefault| @disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm%R%Q SpwmpclkUGdefault| @disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm%R%Q SpwmpclkUGdefault| @disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm %R%Q SpwmpclkUGdefault| @disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0%R%Q SpwmpclkUGdefault| @disabledtsadc@fec00000rockchip,rk3588-tsadc%%Stsadcapb_pclk%%V%Wytsadc-apbtsadc f } U  Ggpiootpout H adc@fec10000rockchip,rk3588-saradc %%Ssaradcapb_pclk%U ysaradc-apb@okay i2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c%% Si2cpclkCUGdefault+ @disabledi2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c%% Si2cpclkDUGdefault+@okayaudio-codec@11everest,es8316%1Smclk%1portendpointHi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c%% Si2cpclkEUGdefault+ @disabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiJ%%Sspiclkapb_pclkVl l[txrx  UGdefault+ @disabledefuse@fecc0000rockchip,rk3588-otp %%%%Sotpapb_pclkphyarb%%% yotpapbarb+cpu-code@2id@7cpu-leakage@17cpu-leakage@18cpu-leakage@19log-leakage@1agpu-leakage@1bcpu-version@1c npu-leakage@28(codec-leakage@29)dma-controller@fed10000arm,pl330arm,primecell@ Z[%p Sapb_pclk Hlphy@fed80000rockchip,rk3588-usbdp-phy    ,%%l%VSrefclkimmortalpclkutmi(% % % %%yinitcmnlanepcs_apbpma_apb @disableddp-port @disabledusb3-port @disabledH'phy@fee00000rockchip,rk3588-naneng-combphy%%v%W Srefapbpipe%%<%Cyphyapb <4 N @disabledHpphy@fee20000rockchip,rk3588-naneng-combphy%%x%W Srefapbpipe%%>%Eyphyapb <4 N @disabledH2sram@ff001000 mmio-sramL+pinctrlrockchip,rk3588-pinctrlL+Hgpio@fd8a0000rockchip,gpio-bank%q%r  d B Hgpio@fec20000rockchip,gpio-bank%s%t  d B gpio@fec30000rockchip,gpio-bank%u%v  d@ B gpio@fec40000rockchip,gpio-bank%w%x  d` B H|gpio@fec50000rockchip,gpio-bank%y%z  d B Hpcfg-pull-up pHpcfg-pull-none }Hpcfg-pull-none-drv-level-2 } Hpcfg-pull-up-drv-level-1 p Hpcfg-pull-up-drv-level-2 p Hpcfg-pull-none-smt } Hpcfg-output-high Hauddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout Hemmc-bus8 Hemmc-clk Hemmc-cmd Hemmc-data-strobe Heth1fspigmac1gmac1-miim Hvgmac1-rx-bus20  Hxgmac1-tx-bus20    Hwgmac1-rgmii-clk Hygmac1-rgmii-bus@ Hzgpuhdmii2c0i2c0m2-xfer H5i2c1i2c1m0-xfer  Hi2c2i2c2m0-xfer   Hi2c3i2c3m0-xfer   Hi2c4i2c4m0-xfer   Hi2c5i2c5m2-xfer   Hi2c6i2c6m0-xfer   Hi2c7i2c7m0-xfer   Hi2c8i2c8m0-xfer   Hi2s0i2s0-lrck Hi2s0-mclk Hi2s0-sclk Hi2s0-sdi0 Hi2s0-sdo0 Hi2s1i2s1m0-lrck Hi2s1m0-sclk Hi2s1m0-sdi0 Hi2s1m0-sdi1 Hi2s1m0-sdi2 Hi2s1m0-sdi3 Hi2s1m0-sdo0  Hi2s1m0-sdo1  Hi2s1m0-sdo2  Hi2s1m0-sdo3  Hi2s2i2s2m1-lrck Hi2s2m1-sclk  Hi2s2m1-sdi  Hi2s2m1-sdo  Hi2s3i2s3-lrck Hi2s3-sclk Hi2s3-sdi Hi2s3-sdo Hjtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp Hpmupwm0pwm0m0-pins H9pwm1pwm1m0-pins H:pwm2pwm2m0-pins H;pwm3pwm3m1-pins  H<pwm4pwm4m0-pins  Hpwm5pwm5m0-pins Hpwm6pwm6m0-pins  Hpwm7pwm7m0-pins  Hpwm8pwm8m0-pins  Hpwm9pwm9m0-pins  Hpwm10pwm10m0-pins  Hpwm11pwm11m0-pins  Hpwm12pwm12m0-pins  Hpwm13pwm13m0-pins  Hpwm14pwm14m0-pins  Hpwm15pwm15m0-pins  Hrefclksatasata0sata1sata2sdiosdiom1-pins` Hsdmmcsdmmc-bus4@ Hsdmmc-clk H}sdmmc-cmd H~sdmmc-det Hspdif0spdif1spi0spi0m0-pins0 Hspi0m0-cs0 Hspi0m0-cs1 Hspi1spi1m1-pins0 Hspi1m1-cs0 Hspi1m1-cs1 Hspi2spi2m2-pins0  Hspi2m2-cs0 Hspi3spi3m1-pins0  Hspi3m1-cs0 Hspi3m1-cs1 Hspi4spi4m0-pins0 Hspi4m0-cs0 Hspi4m0-cs1 Htsadctsadc-shut Huart0uart0m1-xfer  H8uart1uart1m1-xfer   Huart2uart2m0-xfer  Huart3uart3m1-xfer   Huart4uart4m1-xfer   Huart5uart5m1-xfer   Huart6uart6m1-xfer   Huart7uart7m1-xfer   Huart8uart8m1-xfer   Huart9uart9m1-xfer   Hvopbt656gpio-functsadc-gpio-func Hledsio-led Hpowervcc-5v0-en Hrtl8211frtl8211f-rst H{usbvcc5v0-host-en  Hwifibtwl-reset H+wl-dis H,wl-wake-host H-bt-dis H.bt-wake-host H/aliases /mmc@fe2e0000 /mmc@fe2c0000 /serial@feb50000analog-soundaudio-graph-card rk3588-es8316) MicrophoneMic JackHeadphoneHeadphones. MIC2Mic JackHeadphonesHPOLHeadphonesHPOR chosen serial2:1500000n8leds gpio-ledsGdefaultUio-led  status | heartbeatpwm-fanpwm-fan _ , 7Pvcc12v-dcin-regulatorregulator-fixed vcc12v_dcinHvcc5v0-host-regulatorregulator-fixed vcc5v0_hostLK@LK@ < O GdefaultU26H3vcc5v0-sys-regulatorregulator-fixed vcc5v0_sysLK@LK@2H6vcc-5v0-regulatorregulator-fixedvcc_5v0LK@LK@ < OGdefaultU26Hvcc-1v1-nldo-s3-regulatorregulator-fixedvcc_1v1_nldo_s326H compatibleinterrupt-parent#address-cells#size-cellsmodelopp-sharedphandleopp-hzopp-microvoltclock-latency-nsopp-suspendrockchip,grfrockchip,volt-mem-read-marginrockchip,reboot-freqcpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratesoperating-points-v2cpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellscpu-supplyentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namespolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributioninterrupt-namesrangesclock-namesdr_modephysphy-namesphy_typepower-domainsresetssnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirkstatuspinctrl-namespinctrl-0snps,dis_rxdet_inp3_quirkreset-names#phy-cellsphy-supplyfcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspenddmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesreg-namesinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modetx_delayrx_delayreset-assert-usreset-deassert-usreset-gpiossnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeedcd-gpiosdisable-wpno-sdiono-mmcsd-uhs-sdr104vmmc-supplyvqmmc-supplyno-sdnon-removablemmc-hs400-1_8vmmc-hs400-enhanced-stroberockchip,trcm-sync-tx-onlydai-formatmclk-fsremote-endpointmbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellspagesizenum-csspi-max-frequencyvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplygpio-controller#gpio-cellspinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-on-in-suspendrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsvref-supplybitsrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfrockchip,vo-grfrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesbias-pull-upbias-disabledrive-strengthinput-schmitt-enableoutput-highrockchip,pinsmmc0mmc1serial2labelwidgetsroutingdaisstdout-pathcolorlinux,default-triggercooling-levelsfan-supplypwmsenable-active-highgpio