8( &$xunlong,orangepi-5rockchip,rk3588s +7Xunlong Orange Pi 5opp-table-cluster0operating-points-v2=H opp-408000000PQW q q~ q q~e@vopp-600000000P#FW q q~ q q~e@opp-816000000P0,W q q~ q q~e@opp-1008000000P<W q q~ q q~e@opp-1200000000PGW X X~ X X~e@opp-1416000000PTfrW ~ ~e@opp-1608000000P_"W Y Y~ Y Y~e@opp-1800000000PkIW~~~~~~e@opp-table-cluster1operating-points-v2=  H LkIHopp-408000000PQW ' 'B@ L LB@e@vopp-600000000P#FW ' 'B@ L LB@e@opp-816000000P0,W ' 'B@ L LB@e@opp-1008000000P<W h hB@ L LB@e@opp-1200000000PGW  B@ L LB@e@opp-1416000000PTfrW L LB@ L LB@e@opp-1608000000P_"W ` `B@ ` `B@e@opp-1800000000PkIW X XB@ X XB@e@opp-2016000000Px)W P PB@ P PB@e@opp-2208000000PhWHHB@HHB@e@opp-table-cluster2operating-points-v2=  H LkIHopp-408000000PQW ' 'B@ L LB@e@vopp-600000000P#FW ' 'B@ L LB@e@opp-816000000P0,W ' 'B@ L LB@e@opp-1008000000P<W h hB@ L LB@e@opp-1200000000PGW  B@ L LB@e@opp-1416000000PTfrW L LB@ L LB@e@opp-1608000000P_"W ` `B@ ` `B@e@opp-1800000000PkIW X XB@ X XB@e@opp-2016000000Px)W P PB@ P PB@e@opp-2208000000PhWHHB@HHB@e@cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1 cluster2core0 core1 cpu@0cpuarm,cortex-a55psci  0,# 7GT@fs@Hcpu@100cpuarm,cortex-a55psci # 7GT@fs@Hcpu@200cpuarm,cortex-a55psci # 7GT@fs@Hcpu@300cpuarm,cortex-a55psci # 7GT@fs@Hcpu@400cpuarm,cortex-a76psci  0,#7GT@fs@Hcpu@500cpuarm,cortex-a76psci #7GT@fs@H cpu@600cpuarm,cortex-a76psci  0,#7GT@fs@H cpu@700cpuarm,cortex-a76psci #7GT@fs@H idle-statespscicpu-sleeparm,idle-stated*x:Hl2-cache-l0cacheIV@hKWHl2-cache-l1cacheIV@hKWHl2-cache-l2cacheIV@hKWHl2-cache-l3cacheIV@hKWHl2-cache-b0cacheIV@hKWHl2-cache-b1cacheIV@hKWHl2-cache-b2cacheIV@hKWHl2-cache-b3cacheIV@hKWHl3-cachecacheI0V@hKWHfirmwareopteelinaro,optee-tzsmcscmi arm,scmi-smcep+protocol@14vH protocol@16pmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0smcclock-0 fixed-clock)׫spllvthermal-zonessoc-thermal4 tripstrip-point-0$passivetrip-point-1LpassiveH!trip-point-28 criticalcooling-mapsmap0!`  /bigcore0-thermal tripstrip-point-0$passivetrip-point-1LpassiveH"trip-point-28 criticalcooling-mapsmap0"  /bigcore1-thermal tripstrip-point-0$passivetrip-point-1LpassiveH#trip-point-28 criticalcooling-mapsmap0# /littlecore-thermal tripstrip-point-0$passivetrip-point-1LpassiveH$trip-point-28 criticalcooling-mapsmap0$0 /center-thermal tripstrip-point-0$passivetrip-point-1Lpassivetrip-point-28 criticalgpu-thermal tripstrip-point-0$passivetrip-point-1Lpassivetrip-point-28 criticalnpu-thermal tripstrip-point-0$passivetrip-point-1Lpassivetrip-point-28 criticaltimerarm,armv8-timerP    %?|power-domain@13 +|power-domain@14(%%%%%@|power-domain@15 %%%%A|power-domain@16%% BCD+|power-domain@17 %%%% EFG|power-domain@21%%%%%%%%%%%%%%%%%% HIJKLMNO+|power-domain@23%C%A%P|power-domain@14 %%%%@|power-domain@15%%%A|power-domain@22%%Q|power-domain@24%[%Z%]RS+|power-domain@258%%%%%%%ZT|power-domain@268%%%%%%%QUV|power-domain@270%%%%%%WXYZ+|power-domain@28 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HWqos@fdf40500rockchip,rk3588-qossyscon HXqos@fdf40600rockchip,rk3588-qossyscon HYqos@fdf40800rockchip,rk3588-qossyscon HZqos@fdf41000rockchip,rk3588-qossyscon H[qos@fdf41100rockchip,rk3588-qossyscon H\qos@fdf60000rockchip,rk3588-qossyscon HBqos@fdf60200rockchip,rk3588-qossyscon HCqos@fdf60400rockchip,rk3588-qossyscon HDqos@fdf61000rockchip,rk3588-qossyscon HEqos@fdf61200rockchip,rk3588-qossyscon HFqos@fdf61400rockchip,rk3588-qossyscon HGqos@fdf62000rockchip,rk3588-qossyscon H@qos@fdf63000rockchip,rk3588-qossyscon0 HAqos@fdf64000rockchip,rk3588-qossyscon@ HPqos@fdf66000rockchip,rk3588-qossyscon` HHqos@fdf66200rockchip,rk3588-qossysconb HIqos@fdf66400rockchip,rk3588-qossyscond HJqos@fdf66600rockchip,rk3588-qossysconf HKqos@fdf66800rockchip,rk3588-qossysconh HLqos@fdf66a00rockchip,rk3588-qossysconj HMqos@fdf66c00rockchip,rk3588-qossysconl HNqos@fdf66e00rockchip,rk3588-qossysconn HOqos@fdf67000rockchip,rk3588-qossysconp HQqos@fdf67200rockchip,rk3588-qossysconr qos@fdf70000rockchip,rk3588-qossyscon H:qos@fdf71000rockchip,rk3588-qossyscon H;qos@fdf72000rockchip,rk3588-qossyscon H7qos@fdf72200rockchip,rk3588-qossyscon" H8qos@fdf72400rockchip,rk3588-qossyscon$ H9qos@fdf80000rockchip,rk3588-qossyscon HTqos@fdf81000rockchip,rk3588-qossyscon HUqos@fdf81200rockchip,rk3588-qossyscon HVqos@fdf82000rockchip,rk3588-qossyscon HRqos@fdf82200rockchip,rk3588-qossyscon" HSpcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcie0?0%C%H%>%M%R%)Saclk_mstaclk_slvaclk_dbipclkauxpipepciPxdefault+ @disabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c%%| Si2cpclk?xdefault+@okayregulator@42rockchip,rk8602B vdd_npu_s0dp~'0regulator-state-mem2i2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c%%} Si2cpclk@xdefault+ @disabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c%%~ Si2cpclkAxdefault+ @disabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c%% Si2cpclkBxdefault+ @disabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer !%T%W Spclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt%d%c Stclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiF%%Sspiclkapb_pclkK11Ptxrx xdefault+ @disabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiG%%Sspiclkapb_pclkK11Ptxrx xdefault+ @disabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiH%%Sspiclkapb_pclkKPtxrxxdefault+@okay% pmic@0rockchip,rk806 defaultxB@0000000 0 0 !0 . ;0 H U b0 n ~dvs1-null-pins gpio_pwrctrl2 pin_fun0Hdvs2-null-pins gpio_pwrctrl2 pin_fun0Hdvs3-null-pins gpio_pwrctrl3 pin_fun0Hregulatorsdcdc-reg1 vdd_gpu_s0dp~0 regulator-state-mem2dcdc-reg2vdd_cpu_lit_s0dp~0Hregulator-state-mem2dcdc-reg3 vdd_log_s0 L q0regulator-state-mem2 qdcdc-reg4 vdd_vdenc_s0dp~0regulator-state-mem2dcdc-reg5 vdd_ddr_s0 L 0regulator-state-mem2 Pdcdc-reg6 vdd2_ddr_s3Hregulator-state-mem dcdc-reg7vdd_2v0_pldo_s30Hregulator-state-mem  dcdc-reg8 vcc_3v3_s32Z2ZHregulator-state-mem  2Zdcdc-reg9 vddq_ddr_s0regulator-state-mem2dcdc-reg10 vcc_1v8_s3w@w@regulator-state-mem  w@pldo-reg1 avcc_1v8_s0w@w@Hregulator-state-mem2pldo-reg2 vcc_1v8_s0w@w@regulator-state-mem2 w@pldo-reg3 avdd_1v2_s0OOregulator-state-mem2pldo-reg4 vcc_3v3_s02Z2Z0regulator-state-mem2pldo-reg5 vccio_sd_s0w@2Z0H}regulator-state-mem2pldo-reg6 pldo6_s3w@w@regulator-state-mem  w@nldo-reg1 vdd_0v75_s3 q qregulator-state-mem  qnldo-reg2vdd_ddr_pll_s0 P Pregulator-state-mem2 Pnldo-reg3 avdd_0v75_s0 q qregulator-state-mem2nldo-reg4 vdd_0v85_s0 P Pregulator-state-mem2nldo-reg5 vdd_0v75_s0 q qregulator-state-mem2spi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiI%%Sspiclkapb_pclkKPtxrx xdefault+ @disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartL%%Sbaudclkapb_pclkK11 PtxrxxdefaultdZ @disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartM%%Sbaudclkapb_pclkK1 1 PtxrxxdefaultdZ@okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartN%%Sbaudclkapb_pclkK1 1 PtxrxxdefaultdZ @disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartO%%Sbaudclkapb_pclkK PtxrxxdefaultdZ @disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartP%%Sbaudclkapb_pclkK PtxrxxdefaultdZ @disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartQ%%Sbaudclkapb_pclkK PtxrxxdefaultdZ @disabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartR%%Sbaudclkapb_pclkKffPtxrxxdefaultdZ @disabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartS%%Sbaudclkapb_pclkKf f PtxrxxdefaultdZ @disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartT%%Sbaudclkapb_pclkKf f PtxrxxdefaultdZ @disabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm%L%K Spwmpclkxdefaultq @disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm%L%K Spwmpclkxdefaultq @disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm %L%K Spwmpclkxdefaultq @disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0%L%K Spwmpclkxdefaultq @disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm%O%N Spwmpclkxdefaultq @disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm%O%N Spwmpclkxdefaultq @disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm %O%N Spwmpclkxdefaultq @disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0%O%N Spwmpclkxdefaultq @disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm%R%Q Spwmpclkxdefaultq @disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm%R%Q Spwmpclkxdefaultq @disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm %R%Q Spwmpclkxdefaultq @disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0%R%Q Spwmpclkxdefaultq @disabledtsadc@fec00000rockchip,rk3588-tsadc%%Stsadcapb_pclk%%V%Watsadc-apbtsadc   x 1 gpiootpout ;@okayH adc@fec10000rockchip,rk3588-saradc Q%%Ssaradcapb_pclk%U asaradc-apb@okay cHi2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c%% Si2cpclkCxdefault+@okayrtc@51haoyu,hym8563Qvhym8563defaultx  oi2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c%% Si2cpclkDxdefault+ @disabledi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c%% Si2cpclkExdefault+ @disabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiJ%%Sspiclkapb_pclkKf fPtxrx xdefault+ @disabledefuse@fecc0000rockchip,rk3588-otp %%%%Sotpapb_pclkphyarb%%% aotpapbarb+cpu-code@2id@7cpu-leakage@17cpu-leakage@18cpu-leakage@19log-leakage@1agpu-leakage@1bcpu-version@1c }npu-leakage@28(codec-leakage@29)dma-controller@fed10000arm,pl330arm,primecell@ Z[%p Sapb_pclkHfphy@fed80000rockchip,rk3588-usbdp-phy    %%l%VSrefclkimmortalpclkutmi(% % % %%ainitcmnlanepcs_apbpma_apb @disableddp-portm @disabledusb3-portm @disabledH'phy@fee00000rockchip,rk3588-naneng-combphy%%v%W Srefapbpipe%m%<%Caphyapb . @okayHjphy@fee20000rockchip,rk3588-naneng-combphy%%x%W Srefapbpipe%m%>%Eaphyapb . @okayH-sram@ff001000 mmio-sramL+pinctrlrockchip,rk3588-pinctrlL+Hgpio@fd8a0000rockchip,gpio-bank%q%r n 7 ~Hgpio@fec20000rockchip,gpio-bank%s%t n 7 ~Hgpio@fec30000rockchip,gpio-bank%u%v n @ 7 ~gpio@fec40000rockchip,gpio-bank%w%x n ` 7 ~Hkgpio@fec50000rockchip,gpio-bank%y%z n 7 ~Hpcfg-pull-up Hpcfg-pull-none Hpcfg-pull-none-drv-level-2  Hpcfg-pull-up-drv-level-1  Hpcfg-pull-up-drv-level-2  Hpcfg-pull-none-smt  )Hauddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout >Hemmc-bus8 >Hemmc-clk >Hemmc-cmd >Hemmc-data-strobe >Heth1fspifspim0-pins` >Hwgmac1gmac1-miim >Hrgmac1-rx-bus20 > Htgmac1-tx-bus20 >   Hsgmac1-rgmii-clk >Hugmac1-rgmii-bus@ >Hvgpuhdmii2c0i2c0m2-xfer >H/i2c1i2c1m0-xfer >  Hi2c2i2c2m0-xfer >  Hi2c3i2c3m0-xfer >  Hi2c4i2c4m0-xfer >  Hi2c5i2c5m0-xfer >  Hi2c6i2c6m3-xfer >  Hi2c7i2c7m0-xfer >  Hi2c8i2c8m0-xfer >  Hi2s0i2s0-lrck >Hi2s0-sclk >Hi2s0-sdi0 >Hi2s0-sdi1 >Hi2s0-sdi2 >Hi2s0-sdi3 >Hi2s0-sdo0 >Hi2s0-sdo1 >Hi2s0-sdo2 >Hi2s0-sdo3 >Hi2s1i2s1m0-lrck >Hi2s1m0-sclk >Hi2s1m0-sdi0 >Hi2s1m0-sdi1 >Hi2s1m0-sdi2 >Hi2s1m0-sdi3 >Hi2s1m0-sdo0 > Hi2s1m0-sdo1 > Hi2s1m0-sdo2 > Hi2s1m0-sdo3 > Hi2s2i2s2m1-lrck >Hi2s2m1-sclk > Hi2s2m1-sdi > Hi2s2m1-sdo > Hi2s3i2s3-lrck >Hi2s3-sclk >Hi2s3-sdi >Hi2s3-sdo >Hjtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp >Hpmupwm0pwm0m0-pins >H3pwm1pwm1m0-pins >H4pwm2pwm2m0-pins >H5pwm3pwm3m0-pins >H6pwm4pwm4m0-pins > Hpwm5pwm5m0-pins > Hpwm6pwm6m0-pins > Hpwm7pwm7m0-pins > Hpwm8pwm8m0-pins > Hpwm9pwm9m0-pins > Hpwm10pwm10m0-pins > Hpwm11pwm11m0-pins > Hpwm12pwm12m0-pins > Hpwm13pwm13m0-pins > Hpwm14pwm14m0-pins > Hpwm15pwm15m0-pins > Hrefclksatasata0sata1sata2sdiosdiom1-pins` >H~sdmmcsdmmc-bus4@ >H{sdmmc-clk >Hxsdmmc-cmd >Hysdmmc-det >Hzspdif0spdif1spi0spi0m0-pins0 >Hspi0m0-cs0 >Hspi0m0-cs1 >Hspi1spi1m1-pins0 >Hspi1m1-cs0 >Hspi1m1-cs1 >Hspi2spi2m2-pins0 > Hspi2m2-cs0 > Hspi3spi3m1-pins0 > Hspi3m1-cs0 >Hspi3m1-cs1 >Hspi4spi4m0-pins0 >Hspi4m0-cs0 >Hspi4m0-cs1 >Htsadctsadc-shut >Huart0uart0m1-xfer > H2uart1uart1m1-xfer >  Huart2uart2m0-xfer > Huart3uart3m1-xfer >  Huart4uart4m1-xfer >  Huart5uart5m1-xfer >  Huart6uart6m1-xfer >  Huart7uart7m1-xfer >  Huart8uart8m1-xfer >  Huart9uart9m1-xfer >  Hvopbt656gpio-functsadc-gpio-func >Hleds-gpio >Hhym8563hym8563-int >Husb-typecusbc0-int >typec5v-pwren >Haliases L/mmc@fe2c0000 Q/serial@feb50000chosen Yserial2:1500000n8adc-keys adc-keys e qbuttons w@ dbutton-recovery Recovery h leds gpio-ledsdefaultxled-1 R status_led heartbeatvbus-typec-regulatorregulator-fixed  kdefaultx vbus_typecLK@LK@'0vcc5v0-sys-regulatorregulator-fixed vcc5v0_sysLK@LK@H0vcc-3v3-sd-s0-regulatorregulator-fixed  R vcc_3v3_sd_s02Z2Z'H|vcc3v3-pcie20-regulatorregulator-fixed  Rvcc3v3_pcie20w@w@ P'0Hl compatibleinterrupt-parent#address-cells#size-cellsmodelopp-sharedphandleopp-hzopp-microvoltclock-latency-nsopp-suspendrockchip,grfrockchip,volt-mem-read-marginrockchip,reboot-freqcpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratesoperating-points-v2cpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellscpu-supplyentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namespolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributioninterrupt-namesrangesclock-namesdr_modephysphy-namesphy_typepower-domainsresetssnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirkstatussnps,dis_rxdet_inp3_quirkreset-names#phy-cellspinctrl-0pinctrl-namesfcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspenddmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesreg-namesinterrupt-controllerreset-gpiosvpcie3v3-supplyrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modetx_delayreset-assert-usreset-deassert-ussnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxspi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthfifo-depthcap-sd-highspeeddisable-wpno-mmcno-sdiosd-uhs-sdr104vmmc-supplyvqmmc-supplyrockchip,trcm-sync-tx-onlymbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsnum-csvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplygpio-controller#gpio-cellspinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-on-in-suspendrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsvref-supplywakeup-sourcebitsrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfrockchip,vo-grfrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsmmc0serial2stdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltlinux,default-triggerenable-active-highgpioenable-active-lowstartup-delay-us