b8 (  !indiedroid,novarockchip,rk3588s +7Indiedroid Novaopp-table-cluster0operating-points-v2=H opp-408000000PQW q q~ q q~e@vopp-600000000P#FW q q~ q q~e@opp-816000000P0,W q q~ q q~e@opp-1008000000P<W q q~ q q~e@opp-1200000000PGW X X~ X X~e@opp-1416000000PTfrW ~ ~e@opp-1608000000P_"W Y Y~ Y Y~e@opp-1800000000PkIW~~~~~~e@opp-table-cluster1operating-points-v2=  H LkIHopp-408000000PQW ' 'B@ L LB@e@vopp-600000000P#FW ' 'B@ L LB@e@opp-816000000P0,W ' 'B@ L LB@e@opp-1008000000P<W h hB@ L LB@e@opp-1200000000PGW  B@ L LB@e@opp-1416000000PTfrW L LB@ L LB@e@opp-1608000000P_"W ` `B@ ` `B@e@opp-1800000000PkIW X XB@ X XB@e@opp-2016000000Px)W P PB@ P PB@e@opp-2208000000PhWHHB@HHB@e@opp-table-cluster2operating-points-v2=  H LkIHopp-408000000PQW ' 'B@ L LB@e@vopp-600000000P#FW ' 'B@ L LB@e@opp-816000000P0,W ' 'B@ L LB@e@opp-1008000000P<W h hB@ L LB@e@opp-1200000000PGW  B@ L LB@e@opp-1416000000PTfrW L LB@ L LB@e@opp-1608000000P_"W ` `B@ ` `B@e@opp-1800000000PkIW X XB@ X XB@e@opp-2016000000Px)W P PB@ P PB@e@opp-2208000000PhWHHB@HHB@e@cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1 cluster2core0 core1 cpu@0cpuarm,cortex-a55psci  0,# 7GT@fs@Hcpu@100cpuarm,cortex-a55psci # 7GT@fs@Hcpu@200cpuarm,cortex-a55psci # 7GT@fs@Hcpu@300cpuarm,cortex-a55psci # 7GT@fs@Hcpu@400cpuarm,cortex-a76psci  0,#7GT@fs@Hcpu@500cpuarm,cortex-a76psci #7GT@fs@H cpu@600cpuarm,cortex-a76psci  0,#7GT@fs@H cpu@700cpuarm,cortex-a76psci #7GT@fs@H idle-statespscicpu-sleeparm,idle-stated*x:Hl2-cache-l0cacheIV@hKWHl2-cache-l1cacheIV@hKWHl2-cache-l2cacheIV@hKWHl2-cache-l3cacheIV@hKWHl2-cache-b0cacheIV@hKWHl2-cache-b1cacheIV@hKWHl2-cache-b2cacheIV@hKWHl2-cache-b3cacheIV@hKWHl3-cachecacheI0V@hKWHfirmwareopteelinaro,optee-tzsmcscmi arm,scmi-smcep+protocol@14vH protocol@16pmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0smcclock-0 fixed-clock)׫spllvthermal-zonessoc-thermal4 tripstrip-point-0$passivetrip-point-1LpassiveH!trip-point-28 criticalcooling-mapsmap0!`  /bigcore0-thermal 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qos@fdf70000rockchip,rk3588-qossyscon H:qos@fdf71000rockchip,rk3588-qossyscon H;qos@fdf72000rockchip,rk3588-qossyscon H7qos@fdf72200rockchip,rk3588-qossyscon" H8qos@fdf72400rockchip,rk3588-qossyscon$ H9qos@fdf80000rockchip,rk3588-qossyscon HTqos@fdf81000rockchip,rk3588-qossyscon HUqos@fdf81200rockchip,rk3588-qossyscon HVqos@fdf82000rockchip,rk3588-qossyscon HRqos@fdf82200rockchip,rk3588-qossyscon" HSpcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcie0?0%C%H%>%M%R%)Saclk_mstaclk_slvaclk_dbipclkauxpipepciPxdefault+ @disabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c%%| Si2cpclk?xdefault+@okayregulator@42rockchip,rk8602B~dp vdd_npu_s0 '0regulator-state-mem2i2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c%%} Si2cpclk@xdefault+ @disabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c%%~ Si2cpclkAxdefault+ @disabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c%% Si2cpclkBxdefault+ @disabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer !%T%W Spclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt%d%c Stclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiF%%Sspiclkapb_pclkK11Ptxrx xdefault+ @disabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiG%%Sspiclkapb_pclkK11Ptxrx xdefault+ @disabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiH%%Sspiclkapb_pclkKPtxrxxdefault+@okay% pmic@0rockchip,rk806 xdefaultB@000 0 0 0 +0 70 C0 O0 \ i0 v  0dvs1-null-pins gpio_pwrctrl2 pin_fun0Hdvs2-null-pins gpio_pwrctrl2 pin_fun0Hdvs3-null-pins gpio_pwrctrl3 pin_fun0Hregulatorsdcdc-reg1 ~dp vdd_gpu_s00regulator-state-mem2dcdc-reg2~dp0vdd_cpu_lit_s0Hregulator-state-mem2dcdc-reg3 q L vdd_logic_s00regulator-state-mem  qdcdc-reg4~dp vdd_vdenc_s00regulator-state-mem2dcdc-reg5 q P0 vdd_ddr_s0regulator-state-mem2 Pdcdc-reg6 vdd2_ddr_s3regulator-state-mem dcdc-reg7vdd_2v0_pldo_s3Hregulator-state-mem  dcdc-reg82Z2Z vcc_3v3_s3Hsregulator-state-mem  2Zdcdc-reg9 ' ' vddq_ddr_s0regulator-state-mem2dcdc-reg10w@w@ vcc_1v8_s3Hwregulator-state-mem  w@pldo-reg1w@w@ vcc_1v8_s0regulator-state-mem2pldo-reg2w@w@ vcca_1v8_s0regulator-state-mem2 w@pldo-reg3OO vdda_1v2_s0regulator-state-mem2pldo-reg42Z2Z vcca_3v3_s0regulator-state-mem2pldo-reg52Zw@ vccio_sd_s0Htregulator-state-mem2pldo-reg6w@w@vcc_1v8_s3_pldo6regulator-state-mem  w@nldo-reg1 q q vdd_0v75_s3regulator-state-mem  qnldo-reg2 P Pvdda_ddr_pll_s0regulator-state-mem2 Pnldo-reg3 q q avdd_0v75_s0regulator-state-mem2nldo-reg4 P P vdda_0v85_s0regulator-state-mem2nldo-reg5spi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiI%%Sspiclkapb_pclkKPtxrx xdefault+ @disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartL%%Sbaudclkapb_pclkK11 PtxrxxdefaultdZ @disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartM%%Sbaudclkapb_pclkK1 1 PtxrxxdefaultdZ@okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartN%%Sbaudclkapb_pclkK1 1 PtxrxxdefaultdZ @disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartO%%Sbaudclkapb_pclkK PtxrxxdefaultdZ @disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartP%%Sbaudclkapb_pclkK PtxrxxdefaultdZ @disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartQ%%Sbaudclkapb_pclkK PtxrxxdefaultdZ @disabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartR%%Sbaudclkapb_pclkKffPtxrxxdefaultdZ @disabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartS%%Sbaudclkapb_pclkKf f PtxrxxdefaultdZ @disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartT%%Sbaudclkapb_pclk xdefaultdZ@okay bluetooth*realtek,rtl8821cs-btrealtek,rtl8723bs-bt   ) xdefaultpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm%L%K Spwmpclkxdefaultq @disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm%L%K Spwmpclkxdefaultq @disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm %L%K Spwmpclkxdefaultq @disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0%L%K Spwmpclkxdefaultq @disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm%O%N Spwmpclkxdefaultq @disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm%O%N Spwmpclkxdefaultq @disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm %O%N Spwmpclkxdefaultq @disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0%O%N Spwmpclkxdefaultq @disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm%R%Q Spwmpclkxdefaultq @disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm%R%Q Spwmpclkxdefaultq @disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm %R%Q Spwmpclkxdefaultq @disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0%R%Q Spwmpclkxdefaultq @disabledtsadc@fec00000rockchip,rk3588-tsadc%%Stsadcapb_pclk%%V%Watsadc-apbtsadc 9 P gx  gpiootpout @okayH adc@fec10000rockchip,rk3588-saradc %%Ssaradcapb_pclk%U asaradc-apb @disabledi2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c%% Si2cpclkCxdefault+@okaytypec-portc@22 fcs,fusb302" xdefault connectorusb-c-connector dual USB-C dual sink , d B@rtc@51haoyu,hym8563Qvhym8563 xdefault Hi2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c%% Si2cpclkDxdefault+@okayaudio-codec@11everest,es8388%1 sSmclk%1 ,w 8s 9wportendpointDHi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c%% Si2cpclkExdefault+ @disabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiJ%%Sspiclkapb_pclkKf fPtxrx xdefault+ @disabledefuse@fecc0000rockchip,rk3588-otp %%%%Sotpapb_pclkphyarb%%% aotpapbarb+cpu-code@2id@7cpu-leakage@17cpu-leakage@18cpu-leakage@19log-leakage@1agpu-leakage@1bcpu-version@1c Enpu-leakage@28(codec-leakage@29)dma-controller@fed10000arm,pl330arm,primecell@ Z[%p Sapb_pclkHfphy@fed80000rockchip,rk3588-usbdp-phy J ] n %%l%VSrefclkimmortalpclkutmi(% % % %%ainitcmnlanepcs_apbpma_apb @disableddp-portm @disabledusb3-portm @disabledH'phy@fee00000rockchip,rk3588-naneng-combphy%%v%W Srefapbpipe%m%<%Caphyapb .  @disabledHjphy@fee20000rockchip,rk3588-naneng-combphy%%x%W Srefapbpipe%m%>%Eaphyapb .  @disabledH-sram@ff001000 mmio-sramL+pinctrlrockchip,rk3588-pinctrlL+Hgpio@fd8a0000rockchip,gpio-bank%q%r 7: HEADER_12_1v8HEADER_24_1v8Hgpio@fec20000rockchip,gpio-bank%s%t 7 HEADER_27_3v3HEADER_28_3v3HEADER_29_1v8HEADER_7_1v8HEADER_31_1v8HEADER_33_1v8HEADER_11_1v8HEADER_13_1v8HEADER_5_3v3HEADER_3_3v3gpio@fec30000rockchip,gpio-bank%u%v @ 7gpio@fec40000rockchip,gpio-bank%w%x ` 7 HEADER_16_1v8HEADER_18_1v8HEADER_19_1v8HEADER_21_1v8HEADER_23_1v8HEADER_26_1v8HEADER_15_1v8HEADER_22_1v8gpio@fec50000rockchip,gpio-bank%y%z 7 HEADER_37_3v3HEADER_32_3v3HEADER_36_3v3HEADER_35_3v3HEADER_38_3v3HEADER_40_3v3HEADER_8_3v3HEADER_10_3v3Hpcfg-pull-up Hpcfg-pull-down Hpcfg-pull-none Hpcfg-pull-none-drv-level-2  Hpcfg-pull-up-drv-level-1  Hpcfg-pull-up-drv-level-2  Hpcfg-pull-none-smt  Hauddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout %Hxemmc-bus8 %Hyemmc-clk %Hzemmc-cmd %H{emmc-data-strobe %H|eth1fspigmac1gpuhdmii2c0i2c0m2-xfer %H/i2c1i2c1m0-xfer %  Hi2c2i2c2m0-xfer %  Hi2c3i2c3m0-xfer %  Hi2c4i2c4m0-xfer %  Hi2c5i2c5m0-xfer %  Hi2c6i2c6m3-xfer %  Hi2c7i2c7m0-xfer %  Hi2c8i2c8m0-xfer %  Hi2s0i2s0-lrck %H~i2s0-mclk %Hi2s0-sclk %Hi2s0-sdi0 %Hi2s0-sdo0 %Hi2s1i2s1m0-lrck %Hi2s1m0-sclk %Hi2s1m0-sdi0 %Hi2s1m0-sdi1 %Hi2s1m0-sdi2 %Hi2s1m0-sdi3 %Hi2s1m0-sdo0 % Hi2s1m0-sdo1 % Hi2s1m0-sdo2 % Hi2s1m0-sdo3 % Hi2s2i2s2m1-lrck %Hi2s2m1-sclk % Hi2s2m1-sdi % Hi2s2m1-sdo % Hi2s3i2s3-lrck %Hi2s3-sclk %Hi2s3-sdi %Hi2s3-sdo %Hjtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp %Hpmupwm0pwm0m0-pins %H3pwm1pwm1m0-pins %H4pwm2pwm2m0-pins %H5pwm3pwm3m0-pins %H6pwm4pwm4m0-pins % Hpwm5pwm5m0-pins % Hpwm6pwm6m0-pins % Hpwm7pwm7m0-pins % Hpwm8pwm8m0-pins % Hpwm9pwm9m0-pins % Hpwm10pwm10m0-pins % Hpwm11pwm11m0-pins % Hpwm12pwm12m0-pins % Hpwm13pwm13m0-pins % Hpwm14pwm14m0-pins % Hpwm15pwm15m0-pins % Hrefclksatasata0sata1sata2sdiosdiom1-pins` %Husdmmcsdmmc-bus4@ %Hrsdmmc-clk %Hosdmmc-cmd %Hpsdmmc-det %Hqspdif0spdif1spi0spi0m0-pins0 %Hspi0m0-cs0 %Hspi0m0-cs1 %Hspi1spi1m1-pins0 %Hspi1m1-cs0 %Hspi1m1-cs1 %Hspi2spi2m2-pins0 % Hspi2m2-cs0 % Hspi3spi3m1-pins0 % Hspi3m1-cs0 %Hspi3m1-cs1 %Hspi4spi4m0-pins0 %Hspi4m0-cs0 %Hspi4m0-cs1 %Htsadctsadc-shut %Huart0uart0m1-xfer % H2uart1uart1m1-xfer %  Huart2uart2m0-xfer % Huart3uart3m1-xfer %  Huart4uart4m1-xfer %  Huart5uart5m1-xfer %  Huart6uart6m1-xfer %  Huart7uart7m1-xfer %  Huart8uart8m1-xfer %  Huart9uart9m2-xfer %  Huart9m2-ctsn % Huart9m2-rtsn % Hvopbt656gpio-functsadc-gpio-func %Hbluetooth-pinsbt-reset %Hbt-wake-dev %Hbt-wake-host %Hhym8563hym8563-int %Hsdio-pwrseqwifi-enable-h %Husb-typecusbc0-int %Htypec5v-pwren %Haliases 3/mmc@fe2e0000 8/mmc@fe2c0000 =/mmc@fe2d0000 B/serial@feb50000chosen Jserial2:1500000n8sdio-pwrseqmmc-pwrseq-simple Sext_clockxdefault V mHvsoundaudio-graph-card rockchip,es8388-codec) yMicrophoneMic JackHeadphoneHeadphones3 LINPUT2Mic JackHeadphonesLOUT1HeadphonesROUT1 vbus5v0-typec-regulatorregulator-fixed  xdefaultvbus5v0_typecLK@LK@'Hvcc-1v1-nldo-s3-regulatorregulator-fixedvcc_1v1_nldo_s3'0Hvcc-3v3-s0-regulatorregulator-fixed2Z2Z vcc_3v3_s0'sH}regulator-state-mem2vcc5v0-sys-regulatorregulator-fixedLK@LK@ vcc5v0_sysH0vcc5v0-usb-regulatorregulator-fixedLK@LK@ vcc5v0_usb'Hvcc5v0-usbdcin-regulatorregulator-fixedLK@LK@vcc5v0_usbdcinH compatibleinterrupt-parent#address-cells#size-cellsmodelopp-sharedphandleopp-hzopp-microvoltclock-latency-nsopp-suspendrockchip,grfrockchip,volt-mem-read-marginrockchip,reboot-freqcpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratesoperating-points-v2cpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellscpu-supplyentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namespolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributioninterrupt-namesrangesclock-namesdr_modephysphy-namesphy_typepower-domainsresetssnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirkstatussnps,dis_rxdet_inp3_quirkreset-names#phy-cellspinctrl-0pinctrl-namesregulator-always-onregulator-boot-onregulator-max-microvoltregulator-min-microvoltregulator-nameregulator-ramp-delayfcs,suspend-voltage-selectorvin-supplyregulator-off-in-suspenddmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesreg-namesinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpno-sdiono-mmcsd-uhs-sdr104vmmc-supplyvqmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqno-sdnon-removableno-mmc-hs400rockchip,trcm-sync-tx-onlydai-formatmclk-fsremote-endpointmbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsnum-cs#gpio-cellsgpio-controllerspi-max-frequencyvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplypinsfunctionregulator-enable-ramp-delayregulator-on-in-suspendregulator-suspend-microvoltuart-has-rtsctsdevice-wake-gpiosenable-gpioshost-wake-gpiosrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsvbus-supplydata-rolelabelpower-roletry-power-rolesource-pdossink-pdosop-sink-microwattwakeup-sourceAVDD-supplyDVDD-supplyHPVDD-supplybitsrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfrockchip,vo-grfrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesgpio-line-namesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsmmc0mmc1mmc2serial2stdout-pathpost-power-on-delay-msreset-gpioswidgetsroutingdaisenable-active-highgpio