-8"( !radxa,rock-5brockchip,rk3588 +7Radxa ROCK 5 Model Bopp-table-cluster0operating-points-v2=H opp-408000000PQW q q~ q q~e@vopp-600000000P#FW q q~ q q~e@opp-816000000P0,W q q~ q q~e@opp-1008000000P<W q q~ q q~e@opp-1200000000PGW X X~ X X~e@opp-1416000000PTfrW ~ ~e@opp-1608000000P_"W Y Y~ Y Y~e@opp-1800000000PkIW~~~~~~e@opp-table-cluster1operating-points-v2=  H LkIHopp-408000000PQW ' 'B@ L LB@e@vopp-600000000P#FW ' 'B@ L LB@e@opp-816000000P0,W ' 'B@ L LB@e@opp-1008000000P<W h hB@ L LB@e@opp-1200000000PGW  B@ L LB@e@opp-1416000000PTfrW L LB@ L LB@e@opp-1608000000P_"W ` `B@ ` `B@e@opp-1800000000PkIW X XB@ X XB@e@opp-2016000000Px)W P PB@ P PB@e@opp-2208000000PhWHHB@HHB@e@opp-table-cluster2operating-points-v2=  H LkIHopp-408000000PQW ' 'B@ L LB@e@vopp-600000000P#FW ' 'B@ L LB@e@opp-816000000P0,W ' 'B@ L LB@e@opp-1008000000P<W h hB@ L LB@e@opp-1200000000PGW  B@ L LB@e@opp-1416000000PTfrW L LB@ L LB@e@opp-1608000000P_"W ` `B@ ` `B@e@opp-1800000000PkIW X XB@ X XB@e@opp-2016000000Px)W P PB@ P PB@e@opp-2208000000PhWHHB@HHB@e@cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1 cluster2core0 core1 cpu@0cpuarm,cortex-a55psci  0,# 7GT@fs@Hcpu@100cpuarm,cortex-a55psci # 7GT@fs@Hcpu@200cpuarm,cortex-a55psci # 7GT@fs@Hcpu@300cpuarm,cortex-a55psci # 7GT@fs@Hcpu@400cpuarm,cortex-a76psci  0,#7GT@fs@Hcpu@500cpuarm,cortex-a76psci #7GT@fs@H cpu@600cpuarm,cortex-a76psci  0,#7GT@fs@H cpu@700cpuarm,cortex-a76psci #7GT@fs@H idle-statespscicpu-sleeparm,idle-stated*x:Hl2-cache-l0cacheIV@hKWHl2-cache-l1cacheIV@hKWHl2-cache-l2cacheIV@hKWHl2-cache-l3cacheIV@hKWHl2-cache-b0cacheIV@hKWHl2-cache-b1cacheIV@hKWHl2-cache-b2cacheIV@hKWHl2-cache-b3cacheIV@hKWHl3-cachecacheI0V@hKWHfirmwareopteelinaro,optee-tzsmcscmi arm,scmi-smcep+protocol@14vH protocol@16pmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0smcclock-0 fixed-clock)׫spllvthermal-zonessoc-thermal4 tripstrip-point-0$passivetrip-point-1LpassiveH!trip-point-28 criticalcooling-mapsmap0!`  /bigcore0-thermal tripstrip-point-0$passivetrip-point-1LpassiveH"trip-point-28 criticalcooling-mapsmap0"  /bigcore1-thermal tripstrip-point-0$passivetrip-point-1LpassiveH#trip-point-28 criticalcooling-mapsmap0# /littlecore-thermal tripstrip-point-0$passivetrip-point-1LpassiveH$trip-point-28 criticalcooling-mapsmap0$0 /center-thermal tripstrip-point-0$passivetrip-point-1Lpassivetrip-point-28 criticalgpu-thermal tripstrip-point-0$passivetrip-point-1Lpassivetrip-point-28 criticalnpu-thermal tripstrip-point-0$passivetrip-point-1Lpassivetrip-point-28 criticaltimerarm,armv8-timerP    %?@power-domain@13 +power-domain@14(%%%%%Apower-domain@15 %%%%Bpower-domain@16%% CDE+power-domain@17 %%%% FGHpower-domain@21%%%%%%%%%%%%%%%%%% IJKLMNOP+power-domain@23%C%A%Qpower-domain@14 %%%%Apower-domain@15%%%Bpower-domain@22%%Rpower-domain@24%[%Z%]ST+power-domain@258%%%%%%%ZUpower-domain@268%%%%%%%QVWpower-domain@270%%%%%%XYZ[+power-domain@28 %%%%\]power-domain@29(%%%%%^_power-domain@30%z%{`power-domain@318%W%%%%%%abcdpower-domain@33!%W%Z%[power-domain@34"%W%Z%[power-domain@37%%%2epower-domain@38&%4%5power-domain@40(fi2s@fddc0000rockchip,rk3588-i2s-tdm%%%Smclk_txmclk_rxhclk%%Vg[tx(%atx-m @disabledi2s@fddf0000rockchip,rk3588-i2s-tdm%4%4%5Smclk_txmclk_rxhclk%1%Vg[tx(%atx-m @disabledi2s@fddfc000rockchip,rk3588-i2s-tdm%0%0%,Smclk_txmclk_rxhclk%-%Vg[rx(%arx-m @disabledqos@fdf35000rockchip,rk3588-qossysconP H=qos@fdf35200rockchip,rk3588-qossysconR H>qos@fdf35400rockchip,rk3588-qossysconT H?qos@fdf35600rockchip,rk3588-qossysconV H@qos@fdf36000rockchip,rk3588-qossyscon` H`qos@fdf39000rockchip,rk3588-qossyscon Heqos@fdf3d800rockchip,rk3588-qossyscon Hfqos@fdf3e000rockchip,rk3588-qossyscon Hbqos@fdf3e200rockchip,rk3588-qossyscon Haqos@fdf3e400rockchip,rk3588-qossyscon Hcqos@fdf3e600rockchip,rk3588-qossyscon Hdqos@fdf40000rockchip,rk3588-qossyscon H^qos@fdf40200rockchip,rk3588-qossyscon H_qos@fdf40400rockchip,rk3588-qossyscon HXqos@fdf40500rockchip,rk3588-qossyscon HYqos@fdf40600rockchip,rk3588-qossyscon HZqos@fdf40800rockchip,rk3588-qossyscon H[qos@fdf41000rockchip,rk3588-qossyscon H\qos@fdf41100rockchip,rk3588-qossyscon H]qos@fdf60000rockchip,rk3588-qossyscon HCqos@fdf60200rockchip,rk3588-qossyscon HDqos@fdf60400rockchip,rk3588-qossyscon HEqos@fdf61000rockchip,rk3588-qossyscon HFqos@fdf61200rockchip,rk3588-qossyscon HGqos@fdf61400rockchip,rk3588-qossyscon HHqos@fdf62000rockchip,rk3588-qossyscon HAqos@fdf63000rockchip,rk3588-qossyscon0 HBqos@fdf64000rockchip,rk3588-qossyscon@ HQqos@fdf66000rockchip,rk3588-qossyscon` HIqos@fdf66200rockchip,rk3588-qossysconb HJqos@fdf66400rockchip,rk3588-qossyscond HKqos@fdf66600rockchip,rk3588-qossysconf HLqos@fdf66800rockchip,rk3588-qossysconh HMqos@fdf66a00rockchip,rk3588-qossysconj HNqos@fdf66c00rockchip,rk3588-qossysconl HOqos@fdf66e00rockchip,rk3588-qossysconn HPqos@fdf67000rockchip,rk3588-qossysconp HRqos@fdf67200rockchip,rk3588-qossysconr qos@fdf70000rockchip,rk3588-qossyscon H;qos@fdf71000rockchip,rk3588-qossyscon H<qos@fdf72000rockchip,rk3588-qossyscon H8qos@fdf72200rockchip,rk3588-qossyscon" H9qos@fdf72400rockchip,rk3588-qossyscon$ H:qos@fdf80000rockchip,rk3588-qossyscon HUqos@fdf81000rockchip,rk3588-qossyscon HVqos@fdf81200rockchip,rk3588-qossyscon HWqos@fdf82000rockchip,rk3588-qossyscon HSqos@fdf82200rockchip,rk3588-qossyscon" HTpcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcie0?0%C%H%>%M%R%)Saclk_mstaclk_slvaclk_dbipclkauxpipepciPFHi2s@fe480000rockchip,rk3588-i2s-tdmH%y%}%uSmclk_txmclk_rxhclkV22[txrx%^%_ atx-mrx-mdefault( @disabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2sI%%Si2s_clki2s_hclk%%V[txrx(&default @disabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2sJ%%%Si2s_clki2s_hclk%"%V[txrx(&default @disabledinterrupt-controller@fe600000 arm,gic-v3 `h BVa`8kL+Hmsi-controller@fe640000arm,gic-v3-itsdkzHimsi-controller@fe660000arm,gic-v3-itsfkzHppi-partitionsinterrupt-partition-0Hinterrupt-partition-1 Hdma-controller@fea10000arm,pl330arm,primecell@ VW%n Sapb_pclkH2dma-controller@fea30000arm,pl330arm,primecell@ XY%o Sapb_pclkHi2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2c%%{ Si2cpclk>default+ @disabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c%%| Si2cpclk?default+ @disabledi2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c%%} Si2cpclk@default+ @disabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c%%~ Si2cpclkAdefault+ @disabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c%% Si2cpclkBdefault+ @disabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer !%T%W Spclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt%d%c Stclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiF%%Sspiclkapb_pclkV22[txrx default+ @disabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiG%%Sspiclkapb_pclkV22[txrx default+ @disabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiH%%Sspiclkapb_pclkV[txrxdefault+@okay% pmic@0rockchip,rk806B@ tdefault..... . . . ). 5. B O. \ i v.  dvs1-null-pins gpio_pwrctrl2 pin_fun0Hdvs2-null-pins gpio_pwrctrl2 pin_fun0Hdvs3-null-pins gpio_pwrctrl3 pin_fun0Hregulatorsdcdc-reg1dp~0 vdd_gpu_s0 regulator-state-mem=dcdc-reg2dp~0vdd_cpu_lit_s0Hregulator-state-mem=dcdc-reg3 L q0 vdd_log_s0regulator-state-mem= qdcdc-reg4dp~0 vdd_vdenc_s0regulator-state-mem=dcdc-reg5 L 0 vdd_ddr_s0regulator-state-mem= Pdcdc-reg6 vdd2_ddr_s3regulator-state-mem dcdc-reg70vdd_2v0_pldo_s3Hregulator-state-mem  dcdc-reg82Z2Z vcc_3v3_s3Huregulator-state-mem  2Zdcdc-reg9 vddq_ddr_s0regulator-state-mem=dcdc-reg10w@w@ vcc_1v8_s3regulator-state-mem  w@pldo-reg1w@w@ avcc_1v8_s0Hregulator-state-mem=pldo-reg2w@w@ vcc_1v8_s0regulator-state-mem= w@pldo-reg3OO avdd_1v2_s0regulator-state-mem=pldo-reg42Z2Z0 vcc_3v3_s0regulator-state-mem=pldo-reg5w@2Z0 vccio_sd_s0Hvregulator-state-mem=pldo-reg6w@w@ pldo6_s3regulator-state-mem  w@nldo-reg1 q q vdd_0v75_s3regulator-state-mem  qnldo-reg2 P Pvdd_ddr_pll_s0regulator-state-mem= Pnldo-reg3 q q avdd_0v75_s0regulator-state-mem=nldo-reg4 P P vdd_0v85_s0regulator-state-mem=nldo-reg5 q q vdd_0v75_s0regulator-state-mem=spi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiI%%Sspiclkapb_pclkV[txrx default+ @disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartL%%Sbaudclkapb_pclkV22 [txrxdefaultoe @disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartM%%Sbaudclkapb_pclkV2 2 [txrxdefaultoe@okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartN%%Sbaudclkapb_pclkV2 2 [txrxdefaultoe @disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartO%%Sbaudclkapb_pclkV [txrxdefaultoe @disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartP%%Sbaudclkapb_pclkV [txrxdefaultoe @disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartQ%%Sbaudclkapb_pclkV [txrxdefaultoe @disabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartR%%Sbaudclkapb_pclkVgg[txrxdefaultoe @disabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartS%%Sbaudclkapb_pclkVg g [txrxdefaultoe @disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartT%%Sbaudclkapb_pclkVg g [txrxdefaultoe @disabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm%L%K Spwmpclkdefault| @disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm%L%K Spwmpclkdefault| @disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm %L%K Spwmpclkdefault| @disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0%L%K Spwmpclkdefault| @disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm%O%N Spwmpclkdefault| @disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm%O%N Spwmpclkdefault| @disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm %O%N Spwmpclkdefault| @disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0%O%N Spwmpclkdefault| @disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm%R%Q Spwmpclkdefault| @disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm%R%Q Spwmpclkdefault| @disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm %R%Q Spwmpclkdefault| @disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0%R%Q Spwmpclkdefault| @disabledtsadc@fec00000rockchip,rk3588-tsadc%%Stsadcapb_pclk%%V%Watsadc-apbtsadc   * E gpiootpout OH adc@fec10000rockchip,rk3588-saradc e%%Ssaradcapb_pclk%U asaradc-apb@okay wi2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c%% Si2cpclkCdefault+@okayrtc@51haoyu,hym8563Qvhym8563default t i2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c%% Si2cpclkDdefault+@okayaudio-codec@11everest,es8316%1Smclk%1portendpointFHi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c%% Si2cpclkEdefault+ @disabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiJ%%Sspiclkapb_pclkVg g[txrx default+ @disabledefuse@fecc0000rockchip,rk3588-otp %%%%Sotpapb_pclkphyarb%%% aotpapbarb+cpu-code@2id@7cpu-leakage@17cpu-leakage@18cpu-leakage@19log-leakage@1agpu-leakage@1bcpu-version@1c npu-leakage@28(codec-leakage@29)dma-controller@fed10000arm,pl330arm,primecell@ Z[%p Sapb_pclkHgphy@fed80000rockchip,rk3588-usbdp-phy    %%l%VSrefclkimmortalpclkutmi(% % % %%ainitcmnlanepcs_apbpma_apb @disableddp-portm @disabledusb3-portm @disabledH'phy@fee00000rockchip,rk3588-naneng-combphy%%v%W Srefapbpipe%m%<%Caphyapb 0  @disabledHkphy@fee20000rockchip,rk3588-naneng-combphy%%x%W Srefapbpipe%m%>%Eaphyapb 0  @disabledH-sram@ff001000 mmio-sramL+pinctrlrockchip,rk3588-pinctrlL+Hgpio@fd8a0000rockchip,gpio-bank%q%r   B Htgpio@fec20000rockchip,gpio-bank%s%t   B Hgpio@fec30000rockchip,gpio-bank%u%v  @ B gpio@fec40000rockchip,gpio-bank%w%x  ` B gpio@fec50000rockchip,gpio-bank%y%z   B Hpcfg-pull-up Hpcfg-pull-none !Hpcfg-pull-none-drv-level-2 ! .Hpcfg-pull-up-drv-level-1  .Hpcfg-pull-up-drv-level-2  .Hpcfg-pull-none-smt ! =Hauddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout RHxemmc-bus8 RHyemmc-clk RHzemmc-cmd RH{emmc-data-strobe RH|eth1fspigmac1gpuhdmii2c0i2c0m2-xfer RH1i2c1i2c1m0-xfer R  Hi2c2i2c2m0-xfer R  Hi2c3i2c3m0-xfer R  Hi2c4i2c4m0-xfer R  Hi2c5i2c5m0-xfer R  Hi2c6i2c6m0-xfer R  Hi2c7i2c7m0-xfer R  Hi2c8i2c8m0-xfer R  Hi2s0i2s0-lrck RH}i2s0-mclk RH~i2s0-sclk RHi2s0-sdi0 RHi2s0-sdo0 RHi2s1i2s1m0-lrck RHi2s1m0-sclk RHi2s1m0-sdi0 RHi2s1m0-sdi1 RHi2s1m0-sdi2 RHi2s1m0-sdi3 RHi2s1m0-sdo0 R Hi2s1m0-sdo1 R Hi2s1m0-sdo2 R Hi2s1m0-sdo3 R Hi2s2i2s2m1-lrck RHi2s2m1-sclk R Hi2s2m1-sdi R Hi2s2m1-sdo R Hi2s3i2s3-lrck RHi2s3-sclk RHi2s3-sdi RHi2s3-sdo RHjtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp RHpmupwm0pwm0m0-pins RH4pwm1pwm1m0-pins RH5pwm2pwm2m0-pins RH6pwm3pwm3m0-pins RH7pwm4pwm4m0-pins R Hpwm5pwm5m0-pins R Hpwm6pwm6m0-pins R Hpwm7pwm7m0-pins R Hpwm8pwm8m0-pins R Hpwm9pwm9m0-pins R Hpwm10pwm10m0-pins R Hpwm11pwm11m0-pins R Hpwm12pwm12m0-pins R Hpwm13pwm13m0-pins R Hpwm14pwm14m0-pins R Hpwm15pwm15m0-pins R Hrefclksatasata0sata1sata2sdiosdiom1-pins` RHwsdmmcsdmmc-bus4@ RHssdmmc-clk RHpsdmmc-cmd RHqsdmmc-det RHrspdif0spdif1spi0spi0m0-pins0 RHspi0m0-cs0 RHspi0m0-cs1 RHspi1spi1m1-pins0 RHspi1m1-cs0 RHspi1m1-cs1 RHspi2spi2m2-pins0 R Hspi2m2-cs0 R Hspi3spi3m1-pins0 R Hspi3m1-cs0 RHspi3m1-cs1 RHspi4spi4m0-pins0 RHspi4m0-cs0 RHspi4m0-cs1 RHtsadctsadc-shut RHuart0uart0m1-xfer R H3uart1uart1m1-xfer R  Huart2uart2m0-xfer R Huart3uart3m1-xfer R  Huart4uart4m1-xfer R  Huart5uart5m1-xfer R  Huart6uart6m1-xfer R  Huart7uart7m1-xfer R  Huart8uart8m1-xfer R  Huart9uart9m1-xfer R  Hvopbt656gpio-functsadc-gpio-func RHeth0gmac0hym8563hym8563-int RHsoundhp-detect RHusbvcc5v0-host-en RHusb@fc400000rockchip,rk3588-dwc3snps,dwc3@@%%%Sref_clksuspend_clkbus_clk_hostglusb2-phyusb3-phy vutmi_wide(%S @disabledsyscon@fd5b8000%rockchip,rk3588-pcie3-phy-grfsyscon[Hsyscon@fd5c0000$rockchip,rk3588-pipe-phy-grfsyscon\Hsyscon@fd5cc000$rockchip,rk3588-usbdpphy-grfsyscon\@Hsyscon@fd5d4000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@@+Husb2-phy@4000rockchip,rk3588-usb2phy@%n%aphyapb%Sphyclk usb480m_phy1v @disabledHotg-portm @disabledHi2s@fddc8000rockchip,rk3588-i2s-tdm܀%%%Smclk_txmclk_rxhclk%%Vg[tx(%atx-m @disabledi2s@fddf4000rockchip,rk3588-i2s-tdm@%9%9%?Smclk_txmclk_rxhclk%6%Vg[tx(%atx-m @disabledi2s@fddf8000rockchip,rk3588-i2s-tdm߀%+%+%'Smclk_txmclk_rxhclk%(%Vg[rx(%arx-m @disabledi2s@fde00000rockchip,rk3588-i2s-tdm%&%&%"Smclk_txmclk_rxhclk%#%Vg[rx(%arx-m @disabledpcie@fe150000*rockchip,rk3588-pcierockchip,rk3568-pcie+0%@%E%;%J%O%t)Saclk_mstaclk_slvaclk_dbipclkauxpipepciP