: 8,( -,&friendlyarm,nanopc-t6rockchip,rk3588 +7FriendlyElec NanoPC-T6opp-table-cluster0operating-points-v2=H opp-408000000PQW q q~ q q~e@vopp-600000000P#FW q q~ q q~e@opp-816000000P0,W q q~ q q~e@opp-1008000000P<W q q~ q q~e@opp-1200000000PGW X X~ X X~e@opp-1416000000PTfrW ~ ~e@opp-1608000000P_"W Y Y~ Y Y~e@opp-1800000000PkIW~~~~~~e@opp-table-cluster1operating-points-v2=  H LkIHopp-408000000PQW ' 'B@ L LB@e@vopp-600000000P#FW ' 'B@ L LB@e@opp-816000000P0,W ' 'B@ L LB@e@opp-1008000000P<W h hB@ L LB@e@opp-1200000000PGW  B@ L LB@e@opp-1416000000PTfrW L LB@ L LB@e@opp-1608000000P_"W ` `B@ ` `B@e@opp-1800000000PkIW X XB@ X XB@e@opp-2016000000Px)W P PB@ P PB@e@opp-2208000000PhWHHB@HHB@e@opp-table-cluster2operating-points-v2=  H LkIHopp-408000000PQW ' 'B@ L LB@e@vopp-600000000P#FW ' 'B@ L LB@e@opp-816000000P0,W ' 'B@ L LB@e@opp-1008000000P<W h hB@ L LB@e@opp-1200000000PGW  B@ L LB@e@opp-1416000000PTfrW L LB@ L LB@e@opp-1608000000P_"W ` `B@ ` `B@e@opp-1800000000PkIW X XB@ X XB@e@opp-2016000000Px)W P PB@ P PB@e@opp-2208000000PhWHHB@HHB@e@cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1 cluster2core0 core1 cpu@0cpuarm,cortex-a55psci  0,# 7GT@fs@Hcpu@100cpuarm,cortex-a55psci # 7GT@fs@Hcpu@200cpuarm,cortex-a55psci # 7GT@fs@Hcpu@300cpuarm,cortex-a55psci # 7GT@fs@Hcpu@400cpuarm,cortex-a76psci  0,#7GT@fs@Hcpu@500cpuarm,cortex-a76psci #7GT@fs@H cpu@600cpuarm,cortex-a76psci  0,#7GT@fs@H cpu@700cpuarm,cortex-a76psci #7GT@fs@H idle-statespscicpu-sleeparm,idle-stated*x:Hl2-cache-l0cacheIV@hKWHl2-cache-l1cacheIV@hKWHl2-cache-l2cacheIV@hKWHl2-cache-l3cacheIV@hKWHl2-cache-b0cacheIV@hKWHl2-cache-b1cacheIV@hKWHl2-cache-b2cacheIV@hKWHl2-cache-b3cacheIV@hKWHl3-cachecacheI0V@hKWHfirmwareopteelinaro,optee-tzsmcscmi arm,scmi-smcep+protocol@14vH protocol@16pmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0smcclock-0 fixed-clock)׫spllvthermal-zonessoc-thermal4 tripstrip-point-0$passivetrip-point-1LpassiveH!trip-point-28 criticalcooling-mapsmap0!`  /bigcore0-thermal tripstrip-point-0$passivetrip-point-1LpassiveH"trip-point-28 criticalcooling-mapsmap0"  /bigcore1-thermal tripstrip-point-0$passivetrip-point-1LpassiveH#trip-point-28 criticalcooling-mapsmap0# /littlecore-thermal tripstrip-point-0$passivetrip-point-1LpassiveH$trip-point-28 criticalcooling-mapsmap0$0 /center-thermal tripstrip-point-0$passivetrip-point-1Lpassivetrip-point-28 criticalgpu-thermal tripstrip-point-0$passivetrip-point-1Lpassivetrip-point-28 criticalnpu-thermal tripstrip-point-0$passivetrip-point-1Lpassivetrip-point-28 criticaltimerarm,armv8-timerP    %?|power-domain@13 +|power-domain@14(%%%%%@|power-domain@15 %%%%A|power-domain@16%% BCD+|power-domain@17 %%%% EFG|power-domain@21%%%%%%%%%%%%%%%%%% HIJKLMNO+|power-domain@23%C%A%P|power-domain@14 %%%%@|power-domain@15%%%A|power-domain@22%%Q|power-domain@24%[%Z%]RS+|power-domain@258%%%%%%%ZT|power-domain@268%%%%%%%QUV|power-domain@270%%%%%%WXYZ+|power-domain@28 %%%%[\|power-domain@29(%%%%%]^|power-domain@30%z%{_|power-domain@318%W%%%%%%`abc|power-domain@33!%W%Z%[|power-domain@34"%W%Z%[|power-domain@37%%%2d|power-domain@38&%4%5|power-domain@40(e|i2s@fddc0000rockchip,rk3588-i2s-tdm%%%Smclk_txmclk_rxhclk%%KfPtx(%atx-m @disabledi2s@fddf0000rockchip,rk3588-i2s-tdm%4%4%5Smclk_txmclk_rxhclk%1%KfPtx(%atx-m @disabledi2s@fddfc000rockchip,rk3588-i2s-tdm%0%0%,Smclk_txmclk_rxhclk%-%KfPrx(%arx-m @disabledqos@fdf35000rockchip,rk3588-qossysconP H<qos@fdf35200rockchip,rk3588-qossysconR H=qos@fdf35400rockchip,rk3588-qossysconT H>qos@fdf35600rockchip,rk3588-qossysconV H?qos@fdf36000rockchip,rk3588-qossyscon` H_qos@fdf39000rockchip,rk3588-qossyscon Hdqos@fdf3d800rockchip,rk3588-qossyscon Heqos@fdf3e000rockchip,rk3588-qossyscon Haqos@fdf3e200rockchip,rk3588-qossyscon H`qos@fdf3e400rockchip,rk3588-qossyscon Hbqos@fdf3e600rockchip,rk3588-qossyscon Hcqos@fdf40000rockchip,rk3588-qossyscon H]qos@fdf40200rockchip,rk3588-qossyscon H^qos@fdf40400rockchip,rk3588-qossyscon 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qos@fdf70000rockchip,rk3588-qossyscon H:qos@fdf71000rockchip,rk3588-qossyscon H;qos@fdf72000rockchip,rk3588-qossyscon H7qos@fdf72200rockchip,rk3588-qossyscon" H8qos@fdf72400rockchip,rk3588-qossyscon$ H9qos@fdf80000rockchip,rk3588-qossyscon HTqos@fdf81000rockchip,rk3588-qossyscon HUqos@fdf81200rockchip,rk3588-qossyscon HVqos@fdf82000rockchip,rk3588-qossyscon HRqos@fdf82200rockchip,rk3588-qossyscon" HSpcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcie0?0%C%H%>%M%R%)Saclk_mstaclk_slvaclk_dbipclkauxpipepciP M sata@fe230000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci#(%d%a%g%V%qSsatapmaliverxoobrefasic+ @disabledsata-port@01@g- lsata-phy> M spi@fe2b0000 rockchip,sfc+@%/%0Sclk_sfchclk_sfc+ @disabledmmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc,@  %%Sbiuciuciu-driveciu-sample\g defaultxrstu((@okayu}vwmmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc-@ %%%%Sbiuciuciu-driveciu-sample\g defaultxx(% @disabledmmc@fe2e0000rockchip,rk3588-dwcmshc.%-%.%,  n6 (%,%*%+%-%.Scorebusaxiblocktimerg xyz{|}default(%%%%%acorebusaxiblocktimer@okayui2s@fe470000rockchip,rk3588-i2s-tdmG%+%/%(Smclk_txmclk_rxhclk%)%-%%K11Ptxrx(&%*%+ atx-mrx-m defaultx~@okayHportendpoint;i2sFNHi2s@fe480000rockchip,rk3588-i2s-tdmH%y%}%uSmclk_txmclk_rxhclkK11Ptxrx%^%_ atx-mrx-m default(x @disabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2sI%%Si2s_clki2s_hclk%%KPtxrx(& defaultx @disabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2sJ%%%Si2s_clki2s_hclk%"%KPtxrx(& defaultx @disabledinterrupt-controller@fe600000 arm,gic-v3 `h 7^ah8sL+Hmsi-controller@fe640000arm,gic-v3-itsdsHhmsi-controller@fe660000arm,gic-v3-itsfsHppi-partitionsinterrupt-partition-0Hinterrupt-partition-1 Hdma-controller@fea10000arm,pl330arm,primecell@ VW%n Sapb_pclkH1dma-controller@fea30000arm,pl330arm,primecell@ XY%o Sapb_pclkHi2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2c%%{ Si2cpclk>xdefault+ @disabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c%%| Si2cpclk?xdefault+@okayregulator@42rockchip,rk8602B vdd_npu_s0dp~'0regulator-state-mem2i2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c%%} Si2cpclk@xdefault+ @disabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c%%~ Si2cpclkAxdefault+ @disabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c%% Si2cpclkBxdefault+ @disabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer !%T%W Spclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt%d%c Stclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiF%%Sspiclkapb_pclkK11Ptxrx xdefault+ @disabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiG%%Sspiclkapb_pclkK11Ptxrx xdefault+ @disabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiH%%Sspiclkapb_pclkKPtxrxxdefault+@okay% pmic@0rockchip,rk806B@ defaultx00 0 0 #0 /0 ;0 G0 S0 _0 l y0   0  dvs1-null-pins gpio_pwrctrl2 pin_fun0Hdvs2-null-pins gpio_pwrctrl2 pin_fun0Hdvs3-null-pins gpio_pwrctrl3 pin_fun0Hregulatorsdcdc-reg1dp~0 vdd_gpu_s0 regulator-state-mem2dcdc-reg2dp~0vdd_cpu_lit_s0Hregulator-state-mem2dcdc-reg3 L q0 vdd_log_s0regulator-state-mem2 qdcdc-reg4dp~  q0 vdd_vdenc_s0regulator-state-mem2dcdc-reg5 L 0 vdd_ddr_s0regulator-state-mem2 Pdcdc-reg6 vdd2_ddr_s3regulator-state-mem 'dcdc-reg70vdd_2v0_pldo_s3Hregulator-state-mem ' dcdc-reg82Z2Z vcc_3v3_s3Hvregulator-state-mem ' 2Zdcdc-reg9 vddq_ddr_s0regulator-state-mem2dcdc-reg10w@w@ vcc_1v8_s3regulator-state-mem ' w@pldo-reg1w@w@ avcc_1v8_s0Hregulator-state-mem2pldo-reg2w@w@ vcc_1v8_s0regulator-state-mem2 w@pldo-reg3OO avdd_1v2_s0regulator-state-mem2pldo-reg42Z2Z0 vcc_3v3_s0regulator-state-mem2pldo-reg5w@2Z0 vccio_sd_s0Hwregulator-state-mem2pldo-reg6w@w@ pldo6_s3regulator-state-mem ' w@nldo-reg1 q q vdd_0v75_s3regulator-state-mem ' qnldo-reg2 P Pvdd_ddr_pll_s0regulator-state-mem2 Pnldo-reg3 q q avdd_0v75_s0regulator-state-mem2nldo-reg4 P P vdd_0v85_s0regulator-state-mem2nldo-reg5 q q vdd_0v75_s0regulator-state-mem2spi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiI%%Sspiclkapb_pclkKPtxrx xdefault+ @disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartL%%Sbaudclkapb_pclkK11 PtxrxxdefaultdZ @disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartM%%Sbaudclkapb_pclkK1 1 PtxrxxdefaultdZ@okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartN%%Sbaudclkapb_pclkK1 1 PtxrxxdefaultdZ @disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartO%%Sbaudclkapb_pclkK PtxrxxdefaultdZ @disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartP%%Sbaudclkapb_pclkK PtxrxxdefaultdZ @disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartQ%%Sbaudclkapb_pclkK PtxrxxdefaultdZ @disabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartR%%Sbaudclkapb_pclkKffPtxrxxdefaultdZ @disabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartS%%Sbaudclkapb_pclkKf f PtxrxxdefaultdZ @disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartT%%Sbaudclkapb_pclkKf f PtxrxxdefaultdZ @disabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm%L%K Spwmpclkxdefaultq @disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm%L%K Spwmpclkxdefaultq @disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm %L%K Spwmpclkxdefaultq @disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0%L%K Spwmpclkxdefaultq @disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm%O%N Spwmpclkxdefaultq @disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm%O%N Spwmpclkxdefaultq @disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm %O%N Spwmpclkxdefaultq @disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0%O%N Spwmpclkxdefaultq @disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm%R%Q Spwmpclkxdefaultq @disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm%R%Q Spwmpclkxdefaultq @disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm %R%Q Spwmpclkxdefaultq @disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0%R%Q Spwmpclkxdefaultq @disabledtsadc@fec00000rockchip,rk3588-tsadc%%Stsadcapb_pclk%%V%Watsadc-apbtsadc ? V mx  gpiootpout @okayH adc@fec10000rockchip,rk3588-saradc %%Ssaradcapb_pclk%U asaradc-apb@okay i2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c%% Si2cpclkCxdefault+@okay @typec-portc@22 fcs,fusb302" xdefault connectorusb-c-connector dual USB-C dual sink  , B@rtc@51haoyu,hym8563Qvhym8563defaultx  $i2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c%% Si2cpclkDxdefault+@okay @codec@1brealtek,rt5616%1Smclk%1HportendpointNHi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c%% Si2cpclkExdefault+ @disabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiJ%%Sspiclkapb_pclkKf fPtxrx xdefault+ @disabledefuse@fecc0000rockchip,rk3588-otp %%%%Sotpapb_pclkphyarb%%% aotpapbarb+cpu-code@2id@7cpu-leakage@17cpu-leakage@18cpu-leakage@19log-leakage@1agpu-leakage@1bcpu-version@1c 2npu-leakage@28(codec-leakage@29)dma-controller@fed10000arm,pl330arm,primecell@ Z[%p Sapb_pclkHfphy@fed80000rockchip,rk3588-usbdp-phy 7 J [ q%%l%VSrefclkimmortalpclkutmi(% % % %%ainitcmnlanepcs_apbpma_apb @disableddp-portm @disabledusb3-portm @disabledH'phy@fee00000rockchip,rk3588-naneng-combphy%%v%W Srefapbpipe%m%<%Caphyapb . @okayHjphy@fee20000rockchip,rk3588-naneng-combphy%%x%W Srefapbpipe%m%>%Eaphyapb . @okayH-sram@ff001000 mmio-sramL+pinctrlrockchip,rk3588-pinctrlL+Hgpio@fd8a0000rockchip,gpio-bank%q%r  7 ; HEADER_10HEADER_08HEADER_32Hgpio@fec20000rockchip,gpio-bank%s%t  7  HEADER_27HEADER_28HEADER_15HEADER_26HEADER_21HEADER_19HEADER_23HEADER_24HEADER_22HEADER_05HEADER_03Hgpio@fec30000rockchip,gpio-bank%u%v  @ 7 . CSI1_11CSI1_12Hgpio@fec40000rockchip,gpio-bank%w%x  ` 7  HEADER_35HEADER_38HEADER_40HEADER_36HEADER_37DSI0_12HEADER_33DSI0_10HEADER_07HEADER_16HEADER_18HEADER_29HEADER_31HEADER_12DSI0_08DSI0_14HEADER_11HEADER_13DSI1_10gpio@fec50000rockchip,gpio-bank%y%z  7 C DSI1_08DSI1_14DSI1_12CSI0_11CSI0_12Hkpcfg-pull-up Hpcfg-pull-none Hpcfg-pull-none-drv-level-2  Hpcfg-pull-up-drv-level-1  Hpcfg-pull-up-drv-level-2  Hpcfg-pull-none-smt  Hauddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout Hyemmc-bus8 Hzemmc-clk H{emmc-cmd H|emmc-data-strobe H}eth1fspigmac1gpuhdmii2c0i2c0m2-xfer H/i2c1i2c1m0-xfer   Hi2c2i2c2m0-xfer   Hi2c3i2c3m0-xfer   Hi2c4i2c4m0-xfer   Hi2c5i2c5m0-xfer   Hi2c6i2c6m0-xfer   Hi2c7i2c7m0-xfer   Hi2c8i2c8m2-xfer   Hi2s0i2s0-lrck H~i2s0-mclk Hi2s0-sclk Hi2s0-sdi0 Hi2s0-sdo0 Hi2s1i2s1m0-lrck Hi2s1m0-sclk Hi2s1m0-sdi0 Hi2s1m0-sdi1 Hi2s1m0-sdi2 Hi2s1m0-sdi3 Hi2s1m0-sdo0  Hi2s1m0-sdo1  Hi2s1m0-sdo2  Hi2s1m0-sdo3  Hi2s2i2s2m1-lrck Hi2s2m1-sclk  Hi2s2m1-sdi  Hi2s2m1-sdo  Hi2s3i2s3-lrck Hi2s3-sclk Hi2s3-sdi Hi2s3-sdo Hjtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp Hpmupwm0pwm0m0-pins H3pwm1pwm1m1-pins  H4pwm2pwm2m0-pins H5pwm3pwm3m0-pins H6pwm4pwm4m0-pins  Hpwm5pwm5m0-pins  Hpwm6pwm6m0-pins  Hpwm7pwm7m0-pins  Hpwm8pwm8m0-pins  Hpwm9pwm9m0-pins  Hpwm10pwm10m0-pins  Hpwm11pwm11m0-pins  Hpwm12pwm12m0-pins  Hpwm13pwm13m0-pins  Hpwm14pwm14m0-pins  Hpwm15pwm15m0-pins  Hrefclksatasata0sata1sata2sdiosdiom1-pins` Hxsdmmcsdmmc-bus4@ Husdmmc-clk Hrsdmmc-cmd Hssdmmc-det Htspdif0spdif1spi0spi0m0-pins0 Hspi0m0-cs0 Hspi0m0-cs1 Hspi1spi1m1-pins0 Hspi1m1-cs0 Hspi1m1-cs1 Hspi2spi2m2-pins0  Hspi2m2-cs0  Hspi3spi3m1-pins0  Hspi3m1-cs0 Hspi3m1-cs1 Hspi4spi4m0-pins0 Hspi4m0-cs0 Hspi4m0-cs1 Htsadctsadc-shut Huart0uart0m1-xfer  H2uart1uart1m1-xfer   Huart2uart2m0-xfer  Huart3uart3m1-xfer   Huart4uart4m1-xfer   Huart5uart5m1-xfer   Huart6uart6m1-xfer   Huart7uart7m1-xfer   Huart8uart8m1-xfer   Huart9uart9m1-xfer   Hvopbt656gpio-functsadc-gpio-func Heth0gmac0gpio-ledssys-led-pin Husr-led-pin Hheadphonehp-det Hhym8563hym8563-int Hpciepcie2-0-rst  Hpcie2-2-rst Hmpcie-m20-pwren Husbtypec5v-pwren Husbc0-int Husb@fc400000rockchip,rk3588-dwc3snps,dwc3@@%%%Sref_clksuspend_clkbus_clk_hostglusb2-phyusb3-phy vutmi_wide(%S @disabledsyscon@fd5b8000%rockchip,rk3588-pcie3-phy-grfsyscon[Hsyscon@fd5c0000$rockchip,rk3588-pipe-phy-grfsyscon\Hsyscon@fd5cc000$rockchip,rk3588-usbdpphy-grfsyscon\@Hsyscon@fd5d4000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@@+Husb2-phy@4000rockchip,rk3588-usb2phy@%n%aphyapb%Sphyclk usb480m_phy1v @disabledHotg-portm @disabledHi2s@fddc8000rockchip,rk3588-i2s-tdm܀%%%Smclk_txmclk_rxhclk%%KfPtx(%atx-m @disabledi2s@fddf4000rockchip,rk3588-i2s-tdm@%9%9%?Smclk_txmclk_rxhclk%6%KfPtx(%atx-m @disabledi2s@fddf8000rockchip,rk3588-i2s-tdm߀%+%+%'Smclk_txmclk_rxhclk%(%KfPrx(%arx-m @disabledi2s@fde00000rockchip,rk3588-i2s-tdm%&%&%"Smclk_txmclk_rxhclk%#%KfPrx(%arx-m @disabledpcie@fe150000*rockchip,rk3588-pcierockchip,rk3568-pcie+0%@%E%;%J%O%t)Saclk_mstaclk_slvaclk_dbipclkauxpipepciP M phy@fed90000rockchip,rk3588-usbdp-phy 7 J [ q%%m%WSrefclkimmortalpclkutmi(%%%%%ainitcmnlanepcs_apbpma_apb @disableddp-portm @disabledusb3-portm @disabledHphy@fee10000rockchip,rk3588-naneng-combphy%%w%W Srefapbpipe%m%=%Daphyapb . @okayHphy@fee80000rockchip,rk3588-pcie3-phym%ySpclk%Haphy . @okayHaliases "/mmc@fe2e0000 '/mmc@fe2c0000 ,/serial@feb50000chosen 4serial2:1500000n8leds gpio-ledsled-0 R system-led @heartbeatdefaultxled-1 R user-leddefaultxsoundsimple-audio-carddefaultx Vrealtek,rt5616-codec mi2s   Headphones0 HeadphoneHeadphonesMicrophoneMicrophone JackN HeadphonesHPOLHeadphonesHPORMIC1Microphone JackMicrophone Jackmicbias1simple-audio-card,cpu simple-audio-card,codec vcc12v-dcin-regulatorregulator-fixed vcc12v_dcinHvcc5v0-sys-regulatorregulator-fixed vcc5v0_sysLK@LK@'Hvcc4v0-sys-regulatorregulator-fixed vcc4v0_sys= = 'H0vcc-1v1-nldo-s3-regulatorregulator-fixedvcc-1v1-nldo-s3'0Hvcc3v3-pcie20-regulatorregulator-fixedvcc_3v3_pcie202Z2Z'vHlvbus5v0-typec-regulatorregulator-fixed  defaultxvbus5v0_typecLK@LK@'Hvcc3v3-pcie30-regulatorregulator-fixed  Rdefaultxvcc3v3_pcie302Z2Z'H compatibleinterrupt-parent#address-cells#size-cellsmodelopp-sharedphandleopp-hzopp-microvoltclock-latency-nsopp-suspendrockchip,grfrockchip,volt-mem-read-marginrockchip,reboot-freqcpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratesoperating-points-v2cpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellscpu-supplyentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namespolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributioninterrupt-namesrangesclock-namesdr_modephysphy-namesphy_typepower-domainsresetssnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirkstatussnps,dis_rxdet_inp3_quirkreset-names#phy-cellspinctrl-0pinctrl-namesfcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspenddmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesreg-namesinterrupt-controllerreset-gpiosvpcie3v3-supplyrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencyno-sdiono-mmcbus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpsd-uhs-sdr104vmmc-supplyvqmmc-supplyno-sdnon-removablemmc-hs400-1_8vmmc-hs400-enhanced-stroberockchip,trcm-sync-tx-onlydai-formatmclk-fsremote-endpointmbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsrockchip,suspend-voltage-selectornum-csspi-max-frequencyvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplygpio-controller#gpio-cellspinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-init-microvoltregulator-on-in-suspendrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsvref-supplyvbus-supplydata-rolelabelpower-roletry-power-rolesource-pdossink-pdosop-sink-microwattwakeup-sourcebitsrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfrockchip,vo-grfrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesgpio-line-namesbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsrockchip,phy-grfmmc0mmc1serial2stdout-pathlinux,default-triggersimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,hp-det-gpiosimple-audio-card,hp-pin-namesimple-audio-card,widgetssimple-audio-card,routingsound-daienable-active-high