>83H( d3)rockchip,rk3588-evb1-v10rockchip,rk3588 +7Rockchip RK3588 EVB1 V10 Boardopp-table-cluster0operating-points-v2=H opp-408000000PQW q q~ q q~e@vopp-600000000P#FW q q~ q q~e@opp-816000000P0,W q q~ q q~e@opp-1008000000P<W q q~ q q~e@opp-1200000000PGW X X~ X X~e@opp-1416000000PTfrW ~ ~e@opp-1608000000P_"W Y Y~ Y Y~e@opp-1800000000PkIW~~~~~~e@opp-table-cluster1operating-points-v2=  H LkIHopp-408000000PQW ' 'B@ L LB@e@vopp-600000000P#FW ' 'B@ L LB@e@opp-816000000P0,W ' 'B@ L LB@e@opp-1008000000P<W h hB@ L LB@e@opp-1200000000PGW  B@ L LB@e@opp-1416000000PTfrW L LB@ L LB@e@opp-1608000000P_"W ` `B@ ` `B@e@opp-1800000000PkIW X XB@ X XB@e@opp-2016000000Px)W P PB@ P PB@e@opp-2208000000PhWHHB@HHB@e@opp-table-cluster2operating-points-v2=  H LkIHopp-408000000PQW ' 'B@ L LB@e@vopp-600000000P#FW ' 'B@ L LB@e@opp-816000000P0,W ' 'B@ L LB@e@opp-1008000000P<W h hB@ L LB@e@opp-1200000000PGW  B@ L LB@e@opp-1416000000PTfrW L LB@ L LB@e@opp-1608000000P_"W ` `B@ ` `B@e@opp-1800000000PkIW X XB@ X XB@e@opp-2016000000Px)W P PB@ P PB@e@opp-2208000000PhWHHB@HHB@e@cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1 cluster2core0 core1 cpu@0cpuarm,cortex-a55psci  0,# 7GT@fs@Hcpu@100cpuarm,cortex-a55psci # 7GT@fs@Hcpu@200cpuarm,cortex-a55psci # 7GT@fs@Hcpu@300cpuarm,cortex-a55psci # 7GT@fs@Hcpu@400cpuarm,cortex-a76psci  0,#7GT@fs@Hcpu@500cpuarm,cortex-a76psci #7GT@fs@H cpu@600cpuarm,cortex-a76psci  0,#7GT@fs@H cpu@700cpuarm,cortex-a76psci #7GT@fs@H idle-statespscicpu-sleeparm,idle-stated*x:Hl2-cache-l0cacheIV@hKWHl2-cache-l1cacheIV@hKWHl2-cache-l2cacheIV@hKWHl2-cache-l3cacheIV@hKWHl2-cache-b0cacheIV@hKWHl2-cache-b1cacheIV@hKWHl2-cache-b2cacheIV@hKWHl2-cache-b3cacheIV@hKWHl3-cachecacheI0V@hKWHfirmwareopteelinaro,optee-tzsmcscmi arm,scmi-smcep+protocol@14vH protocol@16pmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0smcclock-0 fixed-clock)׫spllvthermal-zonessoc-thermal4 tripstrip-point-0$passivetrip-point-1LpassiveH!trip-point-28 criticalcooling-mapsmap0!`  /bigcore0-thermal tripstrip-point-0$passivetrip-point-1LpassiveH"trip-point-28 criticalcooling-mapsmap0"  /bigcore1-thermal tripstrip-point-0$passivetrip-point-1LpassiveH#trip-point-28 criticalcooling-mapsmap0# /littlecore-thermal tripstrip-point-0$passivetrip-point-1LpassiveH$trip-point-28 criticalcooling-mapsmap0$0 /center-thermal tripstrip-point-0$passivetrip-point-1Lpassivetrip-point-28 criticalgpu-thermal tripstrip-point-0$passivetrip-point-1Lpassivetrip-point-28 criticalnpu-thermal tripstrip-point-0$passivetrip-point-1Lpassivetrip-point-28 criticaltimerarm,armv8-timerP    %?power-domain@13 +power-domain@14(%%%%%@power-domain@15 %%%%Apower-domain@16%% BCD+power-domain@17 %%%% EFGpower-domain@21%%%%%%%%%%%%%%%%%% HIJKLMNO+power-domain@23%C%A%Ppower-domain@14 %%%%@power-domain@15%%%Apower-domain@22%%Qpower-domain@24%[%Z%]RS+power-domain@258%%%%%%%ZTpower-domain@268%%%%%%%QUVpower-domain@270%%%%%%WXYZ+power-domain@28 %%%%[\power-domain@29(%%%%%]^power-domain@30%z%{_power-domain@318%W%%%%%%`abcpower-domain@33!%W%Z%[power-domain@34"%W%Z%[power-domain@37%%%2dpower-domain@38&%4%5power-domain@40(ei2s@fddc0000rockchip,rk3588-i2s-tdm%%%Smclk_txmclk_rxhclk%%ftx(%atx-m @disabledi2s@fddf0000rockchip,rk3588-i2s-tdm%4%4%5Smclk_txmclk_rxhclk%1%ftx(%atx-m @disabledi2s@fddfc000rockchip,rk3588-i2s-tdm%0%0%,Smclk_txmclk_rxhclk%-%frx(%arx-m @disabledqos@fdf35000rockchip,rk3588-qossysconP H<qos@fdf35200rockchip,rk3588-qossysconR H=qos@fdf35400rockchip,rk3588-qossysconT H>qos@fdf35600rockchip,rk3588-qossysconV H?qos@fdf36000rockchip,rk3588-qossyscon` H_qos@fdf39000rockchip,rk3588-qossyscon Hdqos@fdf3d800rockchip,rk3588-qossyscon Heqos@fdf3e000rockchip,rk3588-qossyscon Haqos@fdf3e200rockchip,rk3588-qossyscon H`qos@fdf3e400rockchip,rk3588-qossyscon Hbqos@fdf3e600rockchip,rk3588-qossyscon Hcqos@fdf40000rockchip,rk3588-qossyscon H]qos@fdf40200rockchip,rk3588-qossyscon H^qos@fdf40400rockchip,rk3588-qossyscon HWqos@fdf40500rockchip,rk3588-qossyscon HXqos@fdf40600rockchip,rk3588-qossyscon HYqos@fdf40800rockchip,rk3588-qossyscon HZqos@fdf41000rockchip,rk3588-qossyscon H[qos@fdf41100rockchip,rk3588-qossyscon H\qos@fdf60000rockchip,rk3588-qossyscon HBqos@fdf60200rockchip,rk3588-qossyscon HCqos@fdf60400rockchip,rk3588-qossyscon HDqos@fdf61000rockchip,rk3588-qossyscon HEqos@fdf61200rockchip,rk3588-qossyscon HFqos@fdf61400rockchip,rk3588-qossyscon HGqos@fdf62000rockchip,rk3588-qossyscon H@qos@fdf63000rockchip,rk3588-qossyscon0 HAqos@fdf64000rockchip,rk3588-qossyscon@ HPqos@fdf66000rockchip,rk3588-qossyscon` HHqos@fdf66200rockchip,rk3588-qossysconb HIqos@fdf66400rockchip,rk3588-qossyscond HJqos@fdf66600rockchip,rk3588-qossysconf HKqos@fdf66800rockchip,rk3588-qossysconh HLqos@fdf66a00rockchip,rk3588-qossysconj HMqos@fdf66c00rockchip,rk3588-qossysconl HNqos@fdf66e00rockchip,rk3588-qossysconn HOqos@fdf67000rockchip,rk3588-qossysconp HQqos@fdf67200rockchip,rk3588-qossysconr qos@fdf70000rockchip,rk3588-qossyscon H:qos@fdf71000rockchip,rk3588-qossyscon H;qos@fdf72000rockchip,rk3588-qossyscon H7qos@fdf72200rockchip,rk3588-qossyscon" H8qos@fdf72400rockchip,rk3588-qossyscon$ H9qos@fdf80000rockchip,rk3588-qossyscon HTqos@fdf81000rockchip,rk3588-qossyscon HUqos@fdf81200rockchip,rk3588-qossyscon HVqos@fdf82000rockchip,rk3588-qossyscon HRqos@fdf82200rockchip,rk3588-qossyscon" HSpcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcie0?0%C%H%>%M%R%)Saclk_mstaclk_slvaclk_dbipclkauxpipepciPdefault+ @disabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c%%| Si2cpclk?default+@okayrtc@51haoyu,hym8563Qvhym8563default mi2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c%%} Si2cpclk@default+ @disabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c%%~ Si2cpclkAdefault+ @disabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c%% Si2cpclkBdefault+ @disabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer !%T%W Spclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt%d%c Stclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiF%%Sspiclkapb_pclk11txrx{ default+ @disabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiG%%Sspiclkapb_pclk11txrx{ default+ @disabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiH%%Sspiclkapb_pclktxrx{ default+@okay% pmic@0rockchip,rk806 defaultB@)6CP]dvs1-null-pinsigpio_pwrctrl1 npin_fun0Hdvs2-null-pinsigpio_pwrctrl2 npin_fun0Hdvs3-null-pinsigpio_pwrctrl3 npin_fun0Hregulatorsdcdc-reg1wdp~0 vdd_gpu_s0regulator-state-memdcdc-reg2 wdp~0 vdd_npu_s0regulator-state-memdcdc-reg3 w L q0 vdd_log_s0regulator-state-mem & qdcdc-reg4 wdp~0 vdd_vdenc_s0regulator-state-memdcdc-reg5w L~0vdd_gpu_mem_s0regulator-state-memdcdc-reg6 w L~0vdd_npu_mem_s0regulator-state-memdcdc-reg7 w0vdd_2v0_pldo_s3Hregulator-state-mem B &dcdc-reg8 w L~0vdd_vdenc_mem_s0regulator-state-memdcdc-reg9 w vdd2_ddr_s3regulator-state-mem Bdcdc-reg10 w0vcc_1v1_nldo_s3Hregulator-state-mem B &pldo-reg1 ww@w@0 avcc_1v8_s0regulator-state-mempldo-reg2 ww@w@0vdd1_1v8_ddr_s3regulator-state-mem B &w@pldo-reg3 ww@w@0avcc_1v8_codec_s0regulator-state-mempldo-reg4 w2Z2Z0 vcc_3v3_s3regulator-state-mem B &2Zpldo-reg5 ww@2Z0 vccio_sd_s0regulator-state-mempldo-reg6 ww@w@0 vccio_1v8_s3regulator-state-mem B &w@nldo-reg1 w q q0 vdd_0v75_s3regulator-state-mem B & qnldo-reg2 w  vdd2l_0v9_ddr_s3regulator-state-mem B & nldo-reg3 w q qvdd_0v75_hdmi_edp_s0regulator-state-memnldo-reg4 w q q avdd_0v75_s0regulator-state-memnldo-reg5 w P P vdd_0v85_s0regulator-state-mempmic@1rockchip,rk806  defaultB@)6CP]dvs1-null-pinsigpio_pwrctrl1 npin_fun0Hdvs2-null-pinsigpio_pwrctrl2 npin_fun0Hdvs3-null-pinsigpio_pwrctrl3 npin_fun0Hregulatorsdcdc-reg1 wdp0vdd_cpu_big1_s0Hregulator-state-memdcdc-reg2 wdp0vdd_cpu_big0_s0Hregulator-state-memdcdc-reg3 wdp~0vdd_cpu_lit_s0Hregulator-state-memdcdc-reg4 w2Z2Z0 vcc_3v3_s0regulator-state-memdcdc-reg5 w L0vdd_cpu_big1_mem_s0regulator-state-memdcdc-reg6 w L0vdd_cpu_big0_mem_s0regulator-state-memdcdc-reg7 ww@w@0 vcc_1v8_s0regulator-state-memdcdc-reg8 w L~0vdd_cpu_lit_mem_s0regulator-state-memdcdc-reg9 w vddq_ddr_s0regulator-state-memdcdc-reg10 w L 0 vdd_ddr_s0regulator-state-mempldo-reg1 ww@w@0vcc_1v8_cam_s0regulator-state-mempldo-reg2 ww@w@0avdd1v8_ddr_pll_s0regulator-state-mempldo-reg3 ww@w@0vdd_1v8_pll_s0regulator-state-mempldo-reg4 w2Z2Z0vcc_3v3_sd_s0regulator-state-mempldo-reg5 w**0vcc_2v8_cam_s0regulator-state-mempldo-reg6 ww@w@ pldo6_s3regulator-state-mem B &w@nldo-reg1 w q q0vdd_0v75_pll_s0regulator-state-memnldo-reg2 w P Pvdd_ddr_pll_s0regulator-state-memnldo-reg3 w P P0 avdd_0v85_s0regulator-state-memnldo-reg4 wOO0avdd_1v2_cam_s0regulator-state-memnldo-reg5 wOO0 avdd_1v2_s0regulator-state-memspi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiI%%Sspiclkapb_pclktxrx{ default+ @disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartL%%Sbaudclkapb_pclk11 txrxdefault @disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartM%%Sbaudclkapb_pclk1 1 txrxdefault@okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartN%%Sbaudclkapb_pclk1 1 txrxdefault @disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartO%%Sbaudclkapb_pclk txrxdefault @disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartP%%Sbaudclkapb_pclk txrxdefault @disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartQ%%Sbaudclkapb_pclk txrxdefault @disabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartR%%Sbaudclkapb_pclkfftxrxdefault @disabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartS%%Sbaudclkapb_pclkf f txrxdefault @disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartT%%Sbaudclkapb_pclkf f txrxdefault @disabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm%L%K Spwmpclkdefault @disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm%L%K Spwmpclkdefault @disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm %L%K Spwmpclkdefault @disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0%L%K Spwmpclkdefault @disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm%O%N Spwmpclkdefault @disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm%O%N Spwmpclkdefault @disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm %O%N Spwmpclkdefault @disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0%O%N Spwmpclkdefault @disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm%R%Q Spwmpclkdefault @disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm%R%Q Spwmpclkdefault @disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm %R%Q Spwmpclkdefault @disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0%R%Q Spwmpclkdefault @disabledtsadc@fec00000rockchip,rk3588-tsadc%%Stsadcapb_pclk%%V%Watsadc-apbtsadc Z q   gpiootpout H adc@fec10000rockchip,rk3588-saradc %%Ssaradcapb_pclk%U asaradc-apb @disabledi2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c%% Si2cpclkCdefault+ @disabledi2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c%% Si2cpclkDdefault+ @disabledi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c%% Si2cpclkEdefault+ @disabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiJ%%Sspiclkapb_pclkf ftxrx{ default+ @disabledefuse@fecc0000rockchip,rk3588-otp %%%%Sotpapb_pclkphyarb%%% aotpapbarb+cpu-code@2id@7cpu-leakage@17cpu-leakage@18cpu-leakage@19log-leakage@1agpu-leakage@1bcpu-version@1c npu-leakage@28(codec-leakage@29)dma-controller@fed10000arm,pl330arm,primecell@ Z[K%p Sapb_pclkbHfphy@fed80000rockchip,rk3588-usbdp-phy    %%l%VSrefclkimmortalpclkutmi(% % % %%ainitcmnlanepcs_apbpma_apb @disableddp-portm @disabledusb3-portm @disabledH'phy@fee00000rockchip,rk3588-naneng-combphy%%v%W Srefapbpipe%m%<%Caphyapb $/ 6@okayHjphy@fee20000rockchip,rk3588-naneng-combphy%%x%W Srefapbpipe%m%>%Eaphyapb $/ 6 @disabledH-sram@ff001000 mmio-sramL+pinctrlrockchip,rk3588-pinctrlL+Hgpio@fd8a0000rockchip,gpio-bank%q%r L Hgpio@fec20000rockchip,gpio-bank%s%t L gpio@fec30000rockchip,gpio-bank%u%v L@ gpio@fec40000rockchip,gpio-bank%w%x L` gpio@fec50000rockchip,gpio-bank%y%z L Hpcfg-pull-up XHpcfg-pull-none eHpcfg-pull-none-drv-level-2 e rHpcfg-pull-up-drv-level-1 X rHpcfg-pull-up-drv-level-2 X rHpcfg-pull-none-smt e Hauddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout Htemmc-bus8 Huemmc-clk Hvemmc-cmd Hwemmc-data-strobe Hxeth1fspigmac1gpuhdmii2c0i2c0m0-xfer H0i2c1i2c1m0-xfer  Hi2c2i2c2m0-xfer   Hi2c3i2c3m0-xfer   Hi2c4i2c4m0-xfer   Hi2c5i2c5m0-xfer   Hi2c6i2c6m0-xfer   Hi2c7i2c7m0-xfer   Hi2c8i2c8m0-xfer   Hi2s0i2s0-lrck Hyi2s0-sclk Hzi2s0-sdi0 H{i2s0-sdi1 H|i2s0-sdi2 H}i2s0-sdi3 H~i2s0-sdo0 Hi2s0-sdo1 Hi2s0-sdo2 Hi2s0-sdo3 Hi2s1i2s1m0-lrck Hi2s1m0-sclk Hi2s1m0-sdi0 Hi2s1m0-sdi1 Hi2s1m0-sdi2 Hi2s1m0-sdi3 Hi2s1m0-sdo0  Hi2s1m0-sdo1  Hi2s1m0-sdo2  Hi2s1m0-sdo3  Hi2s2i2s2m1-lrck Hi2s2m1-sclk  Hi2s2m1-sdi  Hi2s2m1-sdo  Hi2s3i2s3-lrck Hi2s3-sclk Hi2s3-sdi Hi2s3-sdo Hjtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp Hpmupwm0pwm0m0-pins H3pwm1pwm1m0-pins H4pwm2pwm2m0-pins H5pwm3pwm3m0-pins H6pwm4pwm4m0-pins  Hpwm5pwm5m0-pins Hpwm6pwm6m0-pins  Hpwm7pwm7m0-pins  Hpwm8pwm8m0-pins  Hpwm9pwm9m0-pins  Hpwm10pwm10m0-pins  Hpwm11pwm11m0-pins  Hpwm12pwm12m0-pins  Hpwm13pwm13m0-pins  Hpwm14pwm14m0-pins  Hpwm15pwm15m0-pins  Hrefclksatasata0sata1sata2sdiosdiom1-pins` Hssdmmcsdmmc-bus4@ Hrsdmmc-clk Hosdmmc-cmd Hpsdmmc-det Hqspdif0spdif1spi0spi0m0-pins0 Hspi0m0-cs0 Hspi0m0-cs1 Hspi1spi1m1-pins0 Hspi1m1-cs0 Hspi1m1-cs1 Hspi2spi2m2-pins0  Hspi2m2-cs0 Hspi2m2-cs1 Hspi3spi3m1-pins0  Hspi3m1-cs0 Hspi3m1-cs1 Hspi4spi4m0-pins0 Hspi4m0-cs0 Hspi4m0-cs1 Htsadctsadc-shut Huart0uart0m1-xfer  H2uart1uart1m1-xfer   Huart2uart2m0-xfer  Huart3uart3m1-xfer   Huart4uart4m1-xfer   Huart5uart5m1-xfer   Huart6uart6m1-xfer   Huart7uart7m1-xfer   Huart8uart8m1-xfer   Huart9uart9m1-xfer   Hvopbt656gpio-functsadc-gpio-func Heth0gmac0gmac0-miim Hgmac0-rx-bus20 Hgmac0-tx-bus20 Hgmac0-rgmii-clk  Hgmac0-rgmii-bus@   Hrtl8211frtl8211f-rst  Hhym8563hym8563-int Husbvcc5v0-host-en Husb@fc400000rockchip,rk3588-dwc3snps,dwc3@@%%%Sref_clksuspend_clkbus_clk_hostglusb2-phyusb3-phy vutmi_wide(%S @disabledsyscon@fd5b8000%rockchip,rk3588-pcie3-phy-grfsyscon[Hsyscon@fd5c0000$rockchip,rk3588-pipe-phy-grfsyscon\Hsyscon@fd5cc000$rockchip,rk3588-usbdpphy-grfsyscon\@Hsyscon@fd5d4000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@@+Husb2-phy@4000rockchip,rk3588-usb2phy@%n%aphyapb%Sphyclk usb480m_phy1v @disabledHotg-portm @disabledHi2s@fddc8000rockchip,rk3588-i2s-tdm܀%%%Smclk_txmclk_rxhclk%%ftx(%atx-m @disabledi2s@fddf4000rockchip,rk3588-i2s-tdm@%9%9%?Smclk_txmclk_rxhclk%6%ftx(%atx-m @disabledi2s@fddf8000rockchip,rk3588-i2s-tdm߀%+%+%'Smclk_txmclk_rxhclk%(%frx(%arx-m @disabledi2s@fde00000rockchip,rk3588-i2s-tdm%&%&%"Smclk_txmclk_rxhclk%#%frx(%arx-m @disabledpcie@fe150000*rockchip,rk3588-pcierockchip,rk3568-pcie+0%@%E%;%J%O%t)Saclk_mstaclk_slvaclk_dbipclkauxpipepciP