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5disabledtsadc@fec00000rockchip,rk3588-tsadc""Htsadcapb_pclk""V"WVtsadc-apbtsadc^um wgpiootpoutHadc@fec10000rockchip,rk3588-saradc""Hsaradcapb_pclk"U Vsaradc-apb 5disabledi2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c"" Hi2cpclkCmwdefault+ 5disabledi2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c"" Hi2cpclkDmwdefault+ 5disabledi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c"" Hi2cpclkEmwdefault+ 5disabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiJ""Hspiclkapb_pclkb btxrxW mwdefault+ 5disabledefuse@fecc0000rockchip,rk3588-otp """"Hotpapb_pclkphyarb""" Votpapbarb+cpu-code@2id@7cpu-leakage@17cpu-leakage@18cpu-leakage@19log-leakage@1agpu-leakage@1bcpu-version@1cnpu-leakage@28(codec-leakage@29)dma-controller@fed10000arm,pl330arm,primecell@ Z[5"p Hapb_pclkLHbphy@fed80000rockchip,rk3588-usbdp-phy""l"VHrefclkimmortalpclkutmi(" " " ""Vinitcmnlanepcs_apbpma_apb 5disableddp-portb 5disabledusb3-portb 5disabledH$phy@fee00000rockchip,rk3588-naneng-combphy""v"W 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Hi2s0i2s0-lrckHui2s0-sclkHvi2s0-sdi0Hwi2s0-sdi1Hxi2s0-sdi2Hyi2s0-sdi3Hzi2s0-sdo0H{i2s0-sdo1H|i2s0-sdo2H}i2s0-sdo3H~i2s1i2s1m0-lrckHi2s1m0-sclkHi2s1m0-sdi0Hi2s1m0-sdi1Hi2s1m0-sdi2Hi2s1m0-sdi3Hi2s1m0-sdo0 Hi2s1m0-sdo1 Hi2s1m0-sdo2 Hi2s1m0-sdo3 Hi2s2i2s2m1-lrckHi2s2m1-sclk Hi2s2m1-sdi Hi2s2m1-sdo Hi2s3i2s3-lrckHi2s3-sclkHi2s3-sdiHi2s3-sdoHjtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmupwm0pwm0m0-pinsH/pwm1pwm1m0-pinsH0pwm2pwm2m0-pinsH1pwm3pwm3m0-pinsH2pwm4pwm4m0-pins Hpwm5pwm5m0-pins Hpwm6pwm6m0-pins Hpwm7pwm7m0-pins Hpwm8pwm8m0-pins Hpwm9pwm9m0-pins Hpwm10pwm10m0-pins Hpwm11pwm11m0-pins Hpwm12pwm12m0-pins Hpwm13pwm13m0-pins Hpwm14pwm14m0-pins Hpwm15pwm15m0-pins Hrefclksatasata0sata1sata2sdiosdiom1-pins`Hosdmmcsdmmc-bus4@Hnsdmmc-clkHksdmmc-cmdHlsdmmc-detHmspdif0spdif1spi0spi0m0-pins0Hspi0m0-cs0Hspi0m0-cs1Hspi1spi1m1-pins0Hspi1m1-cs0Hspi1m1-cs1Hspi2spi2m2-pins0 Hspi2m2-cs0 Hspi2m2-cs1Hspi3spi3m1-pins0 Hspi3m1-cs0Hspi3m1-cs1Hspi4spi4m0-pins0Hspi4m0-cs0Hspi4m0-cs1Htsadctsadc-shutHuart0uart0m1-xfer  H.uart1uart1m1-xfer   Huart2uart2m0-xfer  Huart3uart3m1-xfer   Huart4uart4m1-xfer   Huart5uart5m1-xfer   Huart6uart6m1-xfer   Huart7uart7m1-xfer   Huart8uart8m1-xfer   Huart9uart9m1-xfer   Hvopbt656gpio-functsadc-gpio-funcHeth0gmac0usb@fc400000rockchip,rk3588-dwc3snps,dwc3@@"""Href_clksuspend_clkbus_clkThost\ausb2-phyusb3-phy kutmi_widet%"S 5disabledsyscon@fd5b8000%rockchip,rk3588-pcie3-phy-grfsyscon[Hsyscon@fd5c0000$rockchip,rk3588-pipe-phy-grfsyscon\Hsyscon@fd5cc000$rockchip,rk3588-usbdpphy-grfsyscon\@Hsyscon@fd5d4000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@@+Husb2-phy@4000rockchip,rk3588-usb2phy@"n"Vphyapb"Hphyclk usb480m_phy1k 5disabledHotg-portb 5disabledHi2s@fddc8000rockchip,rk3588-i2s-tdm܀"""Hmclk_txmclk_rxhclk""btxt%"Vtx-m 5disabledi2s@fddf4000rockchip,rk3588-i2s-tdm@"9"9"?Hmclk_txmclk_rxhclk"6"btxt%"Vtx-m 5disabledi2s@fddf8000rockchip,rk3588-i2s-tdm߀"+"+"'Hmclk_txmclk_rxhclk"("brxt%"Vrx-m 5disabledi2s@fde00000rockchip,rk3588-i2s-tdm"&"&""Hmclk_txmclk_rxhclk"#"brxt%"Vrx-m 5disabledpcie@fe150000*rockchip,rk3588-pcierockchip,rk3568-pcie+0"@"E";"J"O"t)Haclk_mstaclk_slvaclk_dbipclkauxpipepciP1syspmcmsglegacyerr`'5FU]\ apcie-phyt%"TA @ @0 @@gdbiapbconfig"&"+ Vpwrpipe 5disabledlegacy-interrupt-controllerq Hpcie@fe160000*rockchip,rk3588-pcierockchip,rk3568-pcie+0"A"F"<"K"P"u)Haclk_mstaclk_slvaclk_dbipclkauxpipepciP1syspmcmsglegacyerr`'5FU]\ apcie-phyt%"TA @ @@0 @@@gdbiapbconfig"'", Vpwrpipe 5disabledlegacy-interrupt-controllerq Hpcie@fe170000*rockchip,rk3588-pcierockchip,rk3568-pcie /0"B"G"="L"Q")Haclk_mstaclk_slvaclk_dbipclkauxpipepciP1syspmcmsglegacyerr`'5FU d ]\ apcie-phyt%"TA @ @0 @@gdbiapbconfig"("- Vpwrpipe+ 5disabledlegacy-interrupt-controllerq Hethernet@fe1b0000&rockchip,rk3588-gmacsnps,dwmac-4.20a 1macirqeth_wake_irq("6"7"X"]"40Hstmmacethclk_mac_refpclk_macaclk_macptp_reft%!"# Vstmmacethg+ 5disabledmdiosnps,dwmac-mdio+stmmac-axi-configHrx-queues-configHqueue0queue1tx-queues-config'Hqueue0queue1sata@fe220000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci"("c"`"f"U"pHsatapmaliverxoobrefasic=+ 5disabledsata-port@0O@\ asata-phy\ k phy@fed90000rockchip,rk3588-usbdp-phy""m"WHrefclkimmortalpclkutmi("""""Vinitcmnlanepcs_apbpma_apb 5disableddp-portb 5disabledusb3-portb 5disabledHphy@fee10000rockchip,rk3588-naneng-combphy""w"W Hrefapbpipe"b"="DVphyapb(+: 5disabledHphy@fee80000rockchip,rk3588-pcie3-phyb"yHpclk"HVphy(+ 5disabledHaliases/mmc@fe2e0000/serial@feb50000vcc12v-dcin-regulatorregulator-fixed vcc12v_dcin   /chosen Gserial2:1500000n8 compatibleinterrupt-parent#address-cells#size-cellsmodelopp-sharedphandleopp-hzopp-microvoltclock-latency-nsopp-suspendrockchip,grfrockchip,volt-mem-read-marginrockchip,reboot-freqcpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratesoperating-points-v2cpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellsentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namespolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributioninterrupt-namesrangesclock-namesdr_modephysphy-namesphy_typepower-domainsresetssnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirkstatussnps,dis_rxdet_inp3_quirkreset-names#phy-cellspinctrl-0pinctrl-namesdmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesreg-namesinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybus-widthno-sdiono-sdnon-removablemmc-hs400-1_8vmmc-hs400-enhanced-stroberockchip,trcm-sync-tx-onlymbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsnum-csrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsbitsrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfrockchip,vo-grfrockchip,pipe-grfrockchip,pipe-phy-grfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsrockchip,phy-grfmmc0serial2regulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltstdout-path