ELFH@@$#_q_@_RB@_q◟"_RB@_ q"_?#{S<@"@5@*`5&@*5@*SA{è#_*!"@@*SA{è#_**!@*SA{è#_*!@"@?#{ <@`"@`@`&@ @R{¨#_?#{ <@`@qHT`2@`.@R @{¨#_`@!?#{CSA8 BV9>@?T@CdjҤtƫ#DE7!C|ěA!|ěc|śD!D` 4QV9>@6@A@q TR9@V@96@BA@|b@HӠ@@@hT@!S2J9B?kT@`~@dB?kTzbcĚHT_q*@ПA8@"BcT{ASB@#_ **@!B@!B?#A8@{"@aB vA8@"BcҡT{B#_?#{SBqT[R*@@6@*qLT @c@ kTskT@*6@*![B@*SA{Ĩ#_[B*SA@{Ĩ#_!?#{B,A!{#_?#{cB{#_?#{cB{#_?#{cB{#_?#{S@>@u@q`T!SA@{è#_`F@`@HA`*@**`"@`@`&@`2@`.@`@SA@{è#_?#{S![b8@ T @cc@*sT"!@cc@*s2T @cc@*T @cc@*B4SAR[B{è#_!@cc@ R! @cc@*sTSAR[B{è#_?#{@@_qT"@#R#_B@RR{#_cc!bXb 9e@%\S@*`*`@b_@`dR\BqT@@@Bq DTSA{¨#_6J9?kT:J9?k!Г!@!@@! s!T@"@@@Rrq2xS0*@@ D:@R@!pSQk(T<S@2 lB@SA{¨#_|@!с qhTA@! *@`@A@@q(T77@@2@c@!?#{ <@`.@`2@`@R` @!Ra@6`@@@?o`@R @R{¨#_?#CA8{SCBo@c@RXs qO%R>*R!R/@@(ST%R!RRR3@HTT#s@M4RHA*M7#s@DMHA*@M7#s@MHA*L7#s@MHA*G7#s@NHA*`G7s#@DNHA*@#7HA!9!@JHA5@44HA!=@ R#@@O4@@O4|@!ҀCC) |@`z!!?AT@s# HA*@F7HA#s*F7#@@As@!š!{ӁOS@(LT!W@(LTSA![@hETc@@@(MT[kBqT@}R!@!@!|3|@i T76R3 9@@@@FT@ @}R@|_ i;T RK5|@ _*TB*q,T@@4@*qTR @B@ k &TkT@*6@*![EkG@!cFsH!@!HA9!@JHA4@!@!cFsHr@}Rғdj @t#R'@||@ x"qT@ B_`T`zbC|ěD{!}?TqBT`_kMBT#3 9@ cT@@@@@)TUF?@@RR@C!@BB @B@@R"R@@!@BB>@@RBR@E!@BBD@@RbR@!C!@BBA@!#@@(2T!@@h2T!'@H2T;#@7XCa6T/@3@#@* %5@*!5'@*@s+5g@R @!R@$@@@? ]@RSW@ I+@,T@!HA*`*5@@%4G4R$R" $RB$R[EcFkGsHyQ @kT6 RK !|@_T߂qZ*$7Q!!@?kT6 ?T@!|![EkG@!@hT##@NsHA* 7@ ^x@c &7@4@R!@R!@R!@R!@R!![@cFsH A8@BB T{C*SDC#_ր@!c@cFsHR?"!@!cFsH@!@!cFsH@!B34cFsH@!#@3@/@[EcFkGsH@!cFsH@![EcFkGsH@!B@!B?@q-T Հ@zt|@`z4Bk TV@!@!cFsHy[EcFkGsHt!@@!3@cFsHf!C@s4!!;@@!K@@!+@!@!@!<[EkG @@!B@[EkG@![EcFkGsH&cFssH"@![EScFkGsH!@!! @!B@B@[EkGi @!@!cFsH[cks@!!@!!c߈c߈c߈c߈c߈c߈B߈߈߈@߈!߈߈C߈߈߈A߈߈A߈߈A߈߈߈ ߈߈A߈߈߈߈e߈`߈@߈B߈A߈`߈A߈@߈c߈߈߈could not enable ref clock: %d could not enable register clock: %d could not enable i2c clock: %d DFLL still enabled while suspending %s: Rate %lu is too low %s: Rate %lu is above dfll range no voltage map entry for %d uV %llu must disable DFLL before removing driver CONTROL REGISTERS: [0x%02x] = 0x%08x I2C and INTR REGISTERS: INTEGRATED I2C CONTROLLER REGISTERS: LUT: cannot disable DFLL in %s mode uninitialized%s: Cannot set DFLL rate in %s mode cannot enable DFLL in %s mode setting disable state failed %s: Cannot unlock DFLL in %s mode %s: Cannot lock DFLL at rate 0 setting enable state failed %s: Cannot lock DFLL in %s mode no tegra_dfll_soc_data provided dfllcouldn't get dfll reset dvcocouldn't get dvco reset nvidia,droop-ctrlfailed to read DT parameter %s: %d nvidia,sample-ratenvidia,force-modenvidia,cfnvidia,cinvidia,cgnvidia,cg-scaleclock-output-namesmissing clock-output-names property nvidia,pwm-to-pmiccouldn't parse device tree parameters Missing step or alignment info for PWM regulatornvidia,pwm-tristate-microvoltscouldn't get initialized voltage nvidia,pwm-period-nanosecondscouldn't get PWM period DT: missing pinctrl device dvfs_pwm_enableDT: missing pwm enabled state dvfs_pwm_disableDT: missing pwm disabled state vdd-cpucouldn't get vdd_cpu regulator nvidia,i2c-fs-rateregulator unsuitable for DFLL I2C operation couldn't get vmax opp, empty opp table? no voltage above DFLL minimum %d mV no opp below DFLL minimum voltage %d mV no voltage map entry rounding to %d uV no opp above DFLL minimum voltage %d mV couldn't build LUT no control register resource couldn't ioremap DFLL control registers no i2c_base resource couldn't ioremap i2c_base resource no i2c_controller_base resource couldn't ioremap i2c_controller_base resource no lut_base resource couldn't ioremap lut_base resource refmissing ref clock socmissing soc clock i2cmissing i2c clock DFLL clock init error unexpected ref clk rate %lu, expecting %lufailed to prepare ref_clk failed to prepare soc_clk failed to prepare i2c_clk DFLL clock registration error of_clk_add_provider() failed DFLL clk registration failed tegra_dfll_fcpuenablelockrateregistersdisabledopen_loopclosed_loop4 y0P drivers/clk/tegra/clk-dfll.cdrivers/clk/tegra/clk-dfll.cdrivers/clk/tegra/clk-dfll.cdrivers/clk/tegra/clk-dfll.cdrivers/clk/tegra/clk-dfll.cdrivers/clk/tegra/clk-dfll.c^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^dfll_calculate_rate_requestdfll_request_ratedfll_unlockdfll_lockaE" AFint i *6u856u32]:6u64w#i HIXp O#E*4=B i G H: I#ie     J;oiw)%)%!)%')%/)%5)%<i#i  @#ii0i.ia i+ i% ii0)i}ei   i        !"#$%&'()*+,-./ iE iu i0i  Xi:I i #i #i!0i"  #i#       V$J ;  i%A  i%e  i%  0i&,   V i'k    i(        !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefgh#i)i*(w    i*<i+  V,;     i-i-),i-9ti-Ni.+    i/(0]i1- i1J    i<82H=dev $2=cvb H$2!$2#  $2$ ($2% 0 iwii<$$$VKp*dev *socp    ( 0z8z@zHzPX`hpxMw% ! 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-fno-delete-null-pointer-checks -fno-allow-store-data-races -fstack-protector-strong -fno-omit-frame-pointer -fno-optimize-sibling-calls -ftrivial-auto-var-init=zero -fno-stack-clash-protection -falign-functions=4 -fstrict-flex-arrays=3 -fno-strict-overflow -fstack-check=no -fconserve-stack -fno-var-tracking -femit-struct-debug-baseonly -fstack-protector-strongNR_ZONE_LRU_BASEPCPU_FC_NRSCHED_SOFTIRQdevices_cgrp_id__kernel_ulong_tNR_PSI_TASK_COUNTSTHP_FAULT_ALLOCNR_INACTIVE_FILEUCOUNT_FANOTIFY_GROUPSACPI_DEVICE_SWNODE_PORT_NUM_ENTRIESdevm_pinctrl_getWMARK_HIGHdfll_clk_hwpwm_pinWORK_OFFQ_LEFTPGPROMOTE_CANDIDATEPGSCAN_KHUGEPAGEDi2c_clientalignmentSWAP_RAdev_pm_opp_putroot__pm_runtime_disable__func__UCOUNT_MNT_NAMESPACESvm_event_item___GFP_COMP_BITdfll_read_monitor_ratedev_pm_opp_find_freq_ceilWORKINGSET_REFAULT_BASEMEMCG_MAXlru_listPGSCAN_SKIP_NORMALPGMIGRATE_SUCCESSNUMA_FOREIGNBALLOON_MIGRATEPGPROMOTE_SUCCESSPSI_MEM_SOME__SD_PREFER_SIBLINGout_minprev_rateSB_FREEZE_COMPLETE__u8v_minCMA_ALLOC_SUCCESSPGDEMOTE_KHUGEPAGEDlast_unrounded_rateNR_FOLL_PIN_ACQUIREDdebugfs_attr_writeNR_MM_COUNTERSWORK_STRUCT_COLOR_BITSUCOUNT_IPC_NAMESPACESNUMA_PAGE_MIGRATEpsi_aggregatorsADDR_NO_RANDOMIZENUMA_OTHERdvco_rstCGROUP_GETSOCKOPTlut_safeNUMA_HUGE_PTE_UPDATESALLOCSTALL_DMA32CGROUP_UNIX_RECVMSGFDPIC_FUNCPTRSinit_clock_trimmersnode_stat_itemi2c_devkmalloc_cache_typepinctrlTHP_FILE_MAPPEDvsel_regUNEVICTABLE_PGCULLEDof_clk_src_simple_getoffsucount_typeNUMA_HIT__UNIQUE_ID_h_611dfll_calculate_rate_requestPGSCAN_KSWAPDTHP_MIGRATION_SPLITpm_runtime_disableMM_SHMEMPAGESsimple_attr_releasedfll_is_runningdvco_target_rateWORKINGSET_RESTORE_FILEssize_ttegra_dfll_runtime_resume__u32__raw_readlUCOUNT_RLIMIT_SIGPENDINGhugetlb_cgrp_idseq_printfMAX_CGROUP_BPF_ATTACH_TYPEMOD_RO_AFTER_INITPGREFILLmin_uvrlimit_typeUCOUNT_RLIMIT_MEMLOCKDQST_CACHE_HITS__SD_SHARE_CPUCAPACITY__seq_putsNR_SHMEM_THPSUNAME26PGSCAN_SKIP_DMA32pinctrl_stateTHP_SWPOUT_FALLBACKdfll_clk_enablepropnameMTHP_STAT_SPLIT_FAILEDreg_uVCGROUP_INET_SOCK_CREATEpsi_reswork_bitsPGLAZYFREEDHTLB_BUDDY_PGALLOCcg_scalelong intdev_pm_opp_get_voltagememory_cgrp_idKSM_SWPIN_COPYWORKINGSET_NODERECLAIMCGROUP_INET6_POST_BINDTHP_SWPOUT__SD_BALANCE_NEWIDLEMIGRATE_CMApdevdev_pm_opp_get_freqset_clock_trimmers_lowPGPGINclass_raw_spinlock_irq_tNR_RUNNINGpwm_enable_stateNR_THROTTLED_WRITTENcvb_tableCGROUP_DEVICEshort unsigned intWORK_OFFQ_DISABLE_BITS___GFP_RECLAIMABLE_BIT__raw_writel__UNIQUE_ID___addressable_tegra_dfll_runtime_resume607last_reqCGROUP_INET6_CONNECTLRU_ACTIVE_FILELRU_UNEVICTABLEMOD_MEM_NUM_TYPESCPUTIME_SYSTEMdevm_reset_control_getNR_FILE_DIRTYclk_preparedfll_scale_dvco_rateCGROUP_INET_INGRESSdfll_i2c_readldfll_clk_opsseq_writeio_cgrp_idclass_raw_spinlock_irqsave_tPGFREENR_ZONE_ACTIVE_FILEWORK_OFFQ_POOL_BITSWORK_OFFQ_BH_BITUNEVICTABLE_PGRESCUEDclk_get_ratesigned charHRTIMER_BASE_REALTIME_SOFTNR_FREE_CMA_PAGESNR_ACTIVE_ANON__u64NR_ISOLATED_FILEtegra_dflldvco_ratefilepm_runtime_get_syncPCPU_FC_EMBEDtegra_dfll_registerpid_typescale__ret_warn_onMTHP_STAT_SWPOUTvec_typescale_bits__TASKSTATS_CMD_MAXunsigned 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