# 0 "arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts"
# 0 "<built-in>"
# 0 "<command-line>"
# 1 "arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts"





/dts-v1/;
# 1 "arch/arm64/boot/dts/rockchip/rk3588.dtsi" 1





# 1 "arch/arm64/boot/dts/rockchip/rk3588s.dtsi" 1





# 1 "./scripts/dtc/include-prefixes/dt-bindings/clock/rockchip,rk3588-cru.h" 1
# 7 "arch/arm64/boot/dts/rockchip/rk3588s.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h" 1
# 9 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h"
# 1 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/irq.h" 1
# 10 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h" 2
# 8 "arch/arm64/boot/dts/rockchip/rk3588s.dtsi" 2

# 1 "./scripts/dtc/include-prefixes/dt-bindings/power/rk3588-power.h" 1
# 10 "arch/arm64/boot/dts/rockchip/rk3588s.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/reset/rockchip,rk3588-cru.h" 1
# 11 "arch/arm64/boot/dts/rockchip/rk3588s.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/phy/phy.h" 1
# 12 "arch/arm64/boot/dts/rockchip/rk3588s.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/ata/ahci.h" 1
# 13 "arch/arm64/boot/dts/rockchip/rk3588s.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/thermal/thermal.h" 1
# 14 "arch/arm64/boot/dts/rockchip/rk3588s.dtsi" 2

/ {
 compatible = "rockchip,rk3588";

 interrupt-parent = <&gic>;
 #address-cells = <2>;
 #size-cells = <2>;

 cluster0_opp_table: opp-table-cluster0 {
  compatible = "operating-points-v2";
  opp-shared;

  opp-408000000 {
   opp-hz = /bits/ 64 <408000000>;
   opp-microvolt = <750000 750000 950000>,
     <750000 750000 950000>;
   clock-latency-ns = <40000>;
   opp-suspend;
  };
  opp-600000000 {
   opp-hz = /bits/ 64 <600000000>;
   opp-microvolt = <750000 750000 950000>,
     <750000 750000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-816000000 {
   opp-hz = /bits/ 64 <816000000>;
   opp-microvolt = <750000 750000 950000>,
     <750000 750000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-1008000000 {
   opp-hz = /bits/ 64 <1008000000>;
   opp-microvolt = <750000 750000 950000>,
     <750000 750000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-1200000000 {
   opp-hz = /bits/ 64 <1200000000>;
   opp-microvolt = <775000 775000 950000>,
     <775000 775000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-1416000000 {
   opp-hz = /bits/ 64 <1416000000>;
   opp-microvolt = <825000 825000 950000>,
     <825000 825000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-1608000000 {
   opp-hz = /bits/ 64 <1608000000>;
   opp-microvolt = <875000 875000 950000>,
     <875000 875000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-1800000000 {
   opp-hz = /bits/ 64 <1800000000>;
   opp-microvolt = <950000 950000 950000>,
     <950000 950000 950000>;
   clock-latency-ns = <40000>;
  };
 };

 cluster1_opp_table: opp-table-cluster1 {
  compatible = "operating-points-v2";
  opp-shared;

  rockchip,grf = <&bigcore0_grf>;
  rockchip,volt-mem-read-margin = <
   855000 1
   765000 2
   675000 3
   495000 4
  >;

  rockchip,reboot-freq = <1800000000>;

  opp-408000000 {
   opp-hz = /bits/ 64 <408000000>;
   opp-microvolt = <600000 600000 1000000>,
     <675000 675000 1000000>;
   clock-latency-ns = <40000>;
   opp-suspend;
  };
  opp-600000000 {
   opp-hz = /bits/ 64 <600000000>;
   opp-microvolt = <600000 600000 1000000>,
     <675000 675000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-816000000 {
   opp-hz = /bits/ 64 <816000000>;
   opp-microvolt = <600000 600000 1000000>,
     <675000 675000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-1008000000 {
   opp-hz = /bits/ 64 <1008000000>;
   opp-microvolt = <625000 625000 1000000>,
     <675000 675000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-1200000000 {
   opp-hz = /bits/ 64 <1200000000>;
   opp-microvolt = <650000 650000 1000000>,
     <675000 675000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-1416000000 {
   opp-hz = /bits/ 64 <1416000000>;
   opp-microvolt = <675000 675000 1000000>,
     <675000 675000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-1608000000 {
   opp-hz = /bits/ 64 <1608000000>;
   opp-microvolt = <700000 700000 1000000>,
     <700000 700000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-1800000000 {
   opp-hz = /bits/ 64 <1800000000>;
   opp-microvolt = <775000 775000 1000000>,
     <775000 775000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-2016000000 {
   opp-hz = /bits/ 64 <2016000000>;
   opp-microvolt = <850000 850000 1000000>,
     <850000 850000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-2208000000 {
   opp-hz = /bits/ 64 <2208000000>;
   opp-microvolt = <925000 925000 1000000>,
     <925000 925000 1000000>;
   clock-latency-ns = <40000>;
  };
 };

 cluster2_opp_table: opp-table-cluster2 {
  compatible = "operating-points-v2";
  opp-shared;

  rockchip,grf = <&bigcore1_grf>;
  rockchip,volt-mem-read-margin = <
   855000 1
   765000 2
   675000 3
   495000 4
  >;

  rockchip,reboot-freq = <1800000000>;

  opp-408000000 {
   opp-hz = /bits/ 64 <408000000>;
   opp-microvolt = <600000 600000 1000000>,
     <675000 675000 1000000>;
   clock-latency-ns = <40000>;
   opp-suspend;
  };
  opp-600000000 {
   opp-hz = /bits/ 64 <600000000>;
   opp-microvolt = <600000 600000 1000000>,
     <675000 675000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-816000000 {
   opp-hz = /bits/ 64 <816000000>;
   opp-microvolt = <600000 600000 1000000>,
     <675000 675000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-1008000000 {
   opp-hz = /bits/ 64 <1008000000>;
   opp-microvolt = <625000 625000 1000000>,
     <675000 675000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-1200000000 {
   opp-hz = /bits/ 64 <1200000000>;
   opp-microvolt = <650000 650000 1000000>,
     <675000 675000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-1416000000 {
   opp-hz = /bits/ 64 <1416000000>;
   opp-microvolt = <675000 675000 1000000>,
     <675000 675000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-1608000000 {
   opp-hz = /bits/ 64 <1608000000>;
   opp-microvolt = <700000 700000 1000000>,
     <700000 700000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-1800000000 {
   opp-hz = /bits/ 64 <1800000000>;
   opp-microvolt = <775000 775000 1000000>,
     <775000 775000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-2016000000 {
   opp-hz = /bits/ 64 <2016000000>;
   opp-microvolt = <850000 850000 1000000>,
     <850000 850000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-2208000000 {
   opp-hz = /bits/ 64 <2208000000>;
   opp-microvolt = <925000 925000 1000000>,
     <925000 925000 1000000>;
   clock-latency-ns = <40000>;
  };
 };

 cpus {
  #address-cells = <1>;
  #size-cells = <0>;

  cpu-map {
   cluster0 {
    core0 {
     cpu = <&cpu_l0>;
    };
    core1 {
     cpu = <&cpu_l1>;
    };
    core2 {
     cpu = <&cpu_l2>;
    };
    core3 {
     cpu = <&cpu_l3>;
    };
   };
   cluster1 {
    core0 {
     cpu = <&cpu_b0>;
    };
    core1 {
     cpu = <&cpu_b1>;
    };
   };
   cluster2 {
    core0 {
     cpu = <&cpu_b2>;
    };
    core1 {
     cpu = <&cpu_b3>;
    };
   };
  };

  cpu_l0: cpu@0 {
   device_type = "cpu";
   compatible = "arm,cortex-a55";
   reg = <0x0>;
   enable-method = "psci";
   capacity-dmips-mhz = <530>;
   clocks = <&scmi_clk 0>;
   assigned-clocks = <&scmi_clk 0>;
   assigned-clock-rates = <816000000>;
   operating-points-v2 = <&cluster0_opp_table>;
   cpu-idle-states = <&CPU_SLEEP>;
   i-cache-size = <32768>;
   i-cache-line-size = <64>;
   i-cache-sets = <128>;
   d-cache-size = <32768>;
   d-cache-line-size = <64>;
   d-cache-sets = <128>;
   next-level-cache = <&l2_cache_l0>;
   dynamic-power-coefficient = <228>;
   #cooling-cells = <2>;
  };

  cpu_l1: cpu@100 {
   device_type = "cpu";
   compatible = "arm,cortex-a55";
   reg = <0x100>;
   enable-method = "psci";
   capacity-dmips-mhz = <530>;
   clocks = <&scmi_clk 0>;
   operating-points-v2 = <&cluster0_opp_table>;
   cpu-idle-states = <&CPU_SLEEP>;
   i-cache-size = <32768>;
   i-cache-line-size = <64>;
   i-cache-sets = <128>;
   d-cache-size = <32768>;
   d-cache-line-size = <64>;
   d-cache-sets = <128>;
   next-level-cache = <&l2_cache_l1>;
   dynamic-power-coefficient = <228>;
   #cooling-cells = <2>;
  };

  cpu_l2: cpu@200 {
   device_type = "cpu";
   compatible = "arm,cortex-a55";
   reg = <0x200>;
   enable-method = "psci";
   capacity-dmips-mhz = <530>;
   clocks = <&scmi_clk 0>;
   operating-points-v2 = <&cluster0_opp_table>;
   cpu-idle-states = <&CPU_SLEEP>;
   i-cache-size = <32768>;
   i-cache-line-size = <64>;
   i-cache-sets = <128>;
   d-cache-size = <32768>;
   d-cache-line-size = <64>;
   d-cache-sets = <128>;
   next-level-cache = <&l2_cache_l2>;
   dynamic-power-coefficient = <228>;
   #cooling-cells = <2>;
  };

  cpu_l3: cpu@300 {
   device_type = "cpu";
   compatible = "arm,cortex-a55";
   reg = <0x300>;
   enable-method = "psci";
   capacity-dmips-mhz = <530>;
   clocks = <&scmi_clk 0>;
   operating-points-v2 = <&cluster0_opp_table>;
   cpu-idle-states = <&CPU_SLEEP>;
   i-cache-size = <32768>;
   i-cache-line-size = <64>;
   i-cache-sets = <128>;
   d-cache-size = <32768>;
   d-cache-line-size = <64>;
   d-cache-sets = <128>;
   next-level-cache = <&l2_cache_l3>;
   dynamic-power-coefficient = <228>;
   #cooling-cells = <2>;
  };

  cpu_b0: cpu@400 {
   device_type = "cpu";
   compatible = "arm,cortex-a76";
   reg = <0x400>;
   enable-method = "psci";
   capacity-dmips-mhz = <1024>;
   clocks = <&scmi_clk 2>;
   assigned-clocks = <&scmi_clk 2>;
   assigned-clock-rates = <816000000>;
   operating-points-v2 = <&cluster1_opp_table>;
   cpu-idle-states = <&CPU_SLEEP>;
   i-cache-size = <65536>;
   i-cache-line-size = <64>;
   i-cache-sets = <256>;
   d-cache-size = <65536>;
   d-cache-line-size = <64>;
   d-cache-sets = <256>;
   next-level-cache = <&l2_cache_b0>;
   dynamic-power-coefficient = <416>;
   #cooling-cells = <2>;
  };

  cpu_b1: cpu@500 {
   device_type = "cpu";
   compatible = "arm,cortex-a76";
   reg = <0x500>;
   enable-method = "psci";
   capacity-dmips-mhz = <1024>;
   clocks = <&scmi_clk 2>;
   operating-points-v2 = <&cluster1_opp_table>;
   cpu-idle-states = <&CPU_SLEEP>;
   i-cache-size = <65536>;
   i-cache-line-size = <64>;
   i-cache-sets = <256>;
   d-cache-size = <65536>;
   d-cache-line-size = <64>;
   d-cache-sets = <256>;
   next-level-cache = <&l2_cache_b1>;
   dynamic-power-coefficient = <416>;
   #cooling-cells = <2>;
  };

  cpu_b2: cpu@600 {
   device_type = "cpu";
   compatible = "arm,cortex-a76";
   reg = <0x600>;
   enable-method = "psci";
   capacity-dmips-mhz = <1024>;
   clocks = <&scmi_clk 3>;
   assigned-clocks = <&scmi_clk 3>;
   assigned-clock-rates = <816000000>;
   operating-points-v2 = <&cluster2_opp_table>;
   cpu-idle-states = <&CPU_SLEEP>;
   i-cache-size = <65536>;
   i-cache-line-size = <64>;
   i-cache-sets = <256>;
   d-cache-size = <65536>;
   d-cache-line-size = <64>;
   d-cache-sets = <256>;
   next-level-cache = <&l2_cache_b2>;
   dynamic-power-coefficient = <416>;
   #cooling-cells = <2>;
  };

  cpu_b3: cpu@700 {
   device_type = "cpu";
   compatible = "arm,cortex-a76";
   reg = <0x700>;
   enable-method = "psci";
   capacity-dmips-mhz = <1024>;
   clocks = <&scmi_clk 3>;
   operating-points-v2 = <&cluster2_opp_table>;
   cpu-idle-states = <&CPU_SLEEP>;
   i-cache-size = <65536>;
   i-cache-line-size = <64>;
   i-cache-sets = <256>;
   d-cache-size = <65536>;
   d-cache-line-size = <64>;
   d-cache-sets = <256>;
   next-level-cache = <&l2_cache_b3>;
   dynamic-power-coefficient = <416>;
   #cooling-cells = <2>;
  };

  idle-states {
   entry-method = "psci";
   CPU_SLEEP: cpu-sleep {
    compatible = "arm,idle-state";
    local-timer-stop;
    arm,psci-suspend-param = <0x0010000>;
    entry-latency-us = <100>;
    exit-latency-us = <120>;
    min-residency-us = <1000>;
   };
  };

  l2_cache_l0: l2-cache-l0 {
   compatible = "cache";
   cache-size = <131072>;
   cache-line-size = <64>;
   cache-sets = <512>;
   cache-level = <2>;
   cache-unified;
   next-level-cache = <&l3_cache>;
  };

  l2_cache_l1: l2-cache-l1 {
   compatible = "cache";
   cache-size = <131072>;
   cache-line-size = <64>;
   cache-sets = <512>;
   cache-level = <2>;
   cache-unified;
   next-level-cache = <&l3_cache>;
  };

  l2_cache_l2: l2-cache-l2 {
   compatible = "cache";
   cache-size = <131072>;
   cache-line-size = <64>;
   cache-sets = <512>;
   cache-level = <2>;
   cache-unified;
   next-level-cache = <&l3_cache>;
  };

  l2_cache_l3: l2-cache-l3 {
   compatible = "cache";
   cache-size = <131072>;
   cache-line-size = <64>;
   cache-sets = <512>;
   cache-level = <2>;
   cache-unified;
   next-level-cache = <&l3_cache>;
  };

  l2_cache_b0: l2-cache-b0 {
   compatible = "cache";
   cache-size = <524288>;
   cache-line-size = <64>;
   cache-sets = <1024>;
   cache-level = <2>;
   cache-unified;
   next-level-cache = <&l3_cache>;
  };

  l2_cache_b1: l2-cache-b1 {
   compatible = "cache";
   cache-size = <524288>;
   cache-line-size = <64>;
   cache-sets = <1024>;
   cache-level = <2>;
   cache-unified;
   next-level-cache = <&l3_cache>;
  };

  l2_cache_b2: l2-cache-b2 {
   compatible = "cache";
   cache-size = <524288>;
   cache-line-size = <64>;
   cache-sets = <1024>;
   cache-level = <2>;
   cache-unified;
   next-level-cache = <&l3_cache>;
  };

  l2_cache_b3: l2-cache-b3 {
   compatible = "cache";
   cache-size = <524288>;
   cache-line-size = <64>;
   cache-sets = <1024>;
   cache-level = <2>;
   cache-unified;
   next-level-cache = <&l3_cache>;
  };

  l3_cache: l3-cache {
   compatible = "cache";
   cache-size = <3145728>;
   cache-line-size = <64>;
   cache-sets = <4096>;
   cache-level = <3>;
   cache-unified;
  };
 };

 firmware {
  optee: optee {
   compatible = "linaro,optee-tz";
   method = "smc";
  };

  scmi: scmi {
   compatible = "arm,scmi-smc";
   arm,smc-id = <0x82000010>;
   shmem = <&scmi_shmem>;
   #address-cells = <1>;
   #size-cells = <0>;

   scmi_clk: protocol@14 {
    reg = <0x14>;
    #clock-cells = <1>;
   };

   scmi_reset: protocol@16 {
    reg = <0x16>;
    #reset-cells = <1>;
   };
  };
 };

 pmu-a55 {
  compatible = "arm,cortex-a55-pmu";
  interrupts = <1 7 4 &ppi_partition0>;
 };

 pmu-a76 {
  compatible = "arm,cortex-a76-pmu";
  interrupts = <1 7 4 &ppi_partition1>;
 };

 psci {
  compatible = "arm,psci-1.0";
  method = "smc";
 };

 spll: clock-0 {
  compatible = "fixed-clock";
  clock-frequency = <702000000>;
  clock-output-names = "spll";
  #clock-cells = <0>;
 };

 thermal_zones: thermal-zones {
  soc_thermal: soc-thermal {
   polling-delay-passive = <20>;
   polling-delay = <1000>;
   sustainable-power = <2100>;

   thermal-sensors = <&tsadc 0>;
   trips {
    trip-point-0 {
     temperature = <75000>;
     hysteresis = <2000>;
     type = "passive";
    };
    soc_target: trip-point-1 {
     temperature = <85000>;
     hysteresis = <2000>;
     type = "passive";
    };
    trip-point-2 {

     temperature = <115000>;

     hysteresis = <2000>;
     type = "critical";
    };
   };

   cooling-maps {
    map0 {
     trip = <&soc_target>;
     cooling-device = <&cpu_l0 (~0) (~0)>,
        <&cpu_l1 (~0) (~0)>,
        <&cpu_l2 (~0) (~0)>,
        <&cpu_l3 (~0) (~0)>,
        <&cpu_b0 (~0) (~0)>,
        <&cpu_b1 (~0) (~0)>,
        <&cpu_b2 (~0) (~0)>,
        <&cpu_b3 (~0) (~0)>;
     contribution = <1024>;
    };
   };
  };

  bigcore0_thermal: bigcore0-thermal {
   polling-delay-passive = <20>;
   polling-delay = <1000>;
   thermal-sensors = <&tsadc 1>;

   trips {
    trip-point-0 {
     temperature = <75000>;
     hysteresis = <2000>;
     type = "passive";
    };
    b0_target: trip-point-1 {
     temperature = <85000>;
     hysteresis = <2000>;
     type = "passive";
    };
    trip-point-2 {

     temperature = <115000>;

     hysteresis = <2000>;
     type = "critical";
    };
   };

   cooling-maps {
    map0 {
     trip = <&b0_target>;
     cooling-device = <&cpu_b0 (~0) (~0)>,
        <&cpu_b1 (~0) (~0)>;
     contribution = <1024>;
    };
   };
  };

  bigcore1_thermal: bigcore1-thermal {
   polling-delay-passive = <20>;
   polling-delay = <1000>;
   thermal-sensors = <&tsadc 2>;
   trips {
    trip-point-0 {
     temperature = <75000>;
     hysteresis = <2000>;
     type = "passive";
    };
    b1_target: trip-point-1 {
     temperature = <85000>;
     hysteresis = <2000>;
     type = "passive";
    };
    trip-point-2 {

     temperature = <115000>;

     hysteresis = <2000>;
     type = "critical";
    };
   };

   cooling-maps {
    map0 {
     trip = <&b1_target>;
     cooling-device = <&cpu_b2 (~0) (~0)>,
        <&cpu_b3 (~0) (~0)>;
     contribution = <1024>;
    };
   };
  };

  little_core_thermal: littlecore-thermal {
   polling-delay-passive = <20>;
   polling-delay = <1000>;
   thermal-sensors = <&tsadc 3>;
   trips {
    trip-point-0 {
     temperature = <75000>;
     hysteresis = <2000>;
     type = "passive";
    };
    l0_target: trip-point-1 {
     temperature = <85000>;
     hysteresis = <2000>;
     type = "passive";
    };
    trip-point-2 {

     temperature = <115000>;

     hysteresis = <2000>;
     type = "critical";
    };
   };

   cooling-maps {
    map0 {
     trip = <&l0_target>;
     cooling-device = <&cpu_l0 (~0) (~0)>,
        <&cpu_l1 (~0) (~0)>,
        <&cpu_l2 (~0) (~0)>,
        <&cpu_l3 (~0) (~0)>;
     contribution = <1024>;
    };
   };
  };

  center_thermal: center-thermal {
   polling-delay-passive = <20>;
   polling-delay = <1000>;
   thermal-sensors = <&tsadc 4>;
   trips {
    trip-point-0 {
     temperature = <75000>;
     hysteresis = <2000>;
     type = "passive";
    };
    trip-point-1 {
     temperature = <85000>;
     hysteresis = <2000>;
     type = "passive";
    };
    trip-point-2 {

     temperature = <115000>;

     hysteresis = <2000>;
     type = "critical";
    };
   };
  };

  gpu_thermal: gpu-thermal {
   polling-delay-passive = <20>;
   polling-delay = <1000>;
   thermal-sensors = <&tsadc 5>;
   trips {
    trip-point-0 {
     temperature = <75000>;
     hysteresis = <2000>;
     type = "passive";
    };
    trip-point-1 {
     temperature = <85000>;
     hysteresis = <2000>;
     type = "passive";
    };
    trip-point-2 {

     temperature = <115000>;

     hysteresis = <2000>;
     type = "critical";
    };
   };
  };

  npu_thermal: npu-thermal {
   polling-delay-passive = <20>;
   polling-delay = <1000>;
   thermal-sensors = <&tsadc 6>;
   trips {
    trip-point-0 {
     temperature = <75000>;
     hysteresis = <2000>;
     type = "passive";
    };
    trip-point-1 {
     temperature = <85000>;
     hysteresis = <2000>;
     type = "passive";
    };
    trip-point-2 {

     temperature = <115000>;

     hysteresis = <2000>;
     type = "critical";
    };
   };
  };
 };

 timer {
  compatible = "arm,armv8-timer";
  interrupts = <1 13 4 0>,
        <1 14 4 0>,
        <1 11 4 0>,
        <1 10 4 0>,
        <1 12 4 0>;
  interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
 };

 xin24m: clock-1 {
  compatible = "fixed-clock";
  clock-frequency = <24000000>;
  clock-output-names = "xin24m";
  #clock-cells = <0>;
 };

 xin32k: clock-2 {
  compatible = "fixed-clock";
  clock-frequency = <32768>;
  clock-output-names = "xin32k";
  #clock-cells = <0>;
 };

 pmu_sram: sram@10f000 {
  compatible = "mmio-sram";
  reg = <0x0 0x0010f000 0x0 0x100>;
  ranges = <0 0x0 0x0010f000 0x100>;
  #address-cells = <1>;
  #size-cells = <1>;

  scmi_shmem: sram@0 {
   compatible = "arm,scmi-shmem";
   reg = <0x0 0x100>;
  };
 };

 usb_host0_xhci: usb@fc000000 {
  compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
  reg = <0x0 0xfc000000 0x0 0x400000>;
  interrupts = <0 220 4 0>;
  clocks = <&cru 404>, <&cru 403>,
    <&cru 402>;
  clock-names = "ref_clk", "suspend_clk", "bus_clk";
  dr_mode = "otg";
  phys = <&u2phy0_otg>, <&usbdp_phy0_u3>;
  phy-names = "usb2-phy", "usb3-phy";
  phy_type = "utmi_wide";
  power-domains = <&power 31>;
  resets = <&cru 338>;
  snps,dis_enblslpm_quirk;
  snps,dis-u1-entry-quirk;
  snps,dis-u2-entry-quirk;
  snps,dis-u2-freeclk-exists-quirk;
  snps,dis-del-phy-power-chg-quirk;
  snps,dis-tx-ipgap-linecheck-quirk;
  status = "disabled";
 };

 usb_host0_ehci: usb@fc800000 {
  compatible = "rockchip,rk3588-ehci", "generic-ehci";
  reg = <0x0 0xfc800000 0x0 0x40000>;
  interrupts = <0 215 4 0>;
  clocks = <&cru 398>, <&cru 399>, <&cru 704>, <&u2phy2>;
  phys = <&u2phy2_host>;
  phy-names = "usb";
  power-domains = <&power 31>;
  status = "disabled";
 };

 usb_host0_ohci: usb@fc840000 {
  compatible = "rockchip,rk3588-ohci", "generic-ohci";
  reg = <0x0 0xfc840000 0x0 0x40000>;
  interrupts = <0 216 4 0>;
  clocks = <&cru 398>, <&cru 399>, <&cru 704>, <&u2phy2>;
  phys = <&u2phy2_host>;
  phy-names = "usb";
  power-domains = <&power 31>;
  status = "disabled";
 };

 usb_host1_ehci: usb@fc880000 {
  compatible = "rockchip,rk3588-ehci", "generic-ehci";
  reg = <0x0 0xfc880000 0x0 0x40000>;
  interrupts = <0 218 4 0>;
  clocks = <&cru 400>, <&cru 401>, <&cru 704>, <&u2phy3>;
  phys = <&u2phy3_host>;
  phy-names = "usb";
  power-domains = <&power 31>;
  status = "disabled";
 };

 usb_host1_ohci: usb@fc8c0000 {
  compatible = "rockchip,rk3588-ohci", "generic-ohci";
  reg = <0x0 0xfc8c0000 0x0 0x40000>;
  interrupts = <0 219 4 0>;
  clocks = <&cru 400>, <&cru 401>, <&cru 704>, <&u2phy3>;
  phys = <&u2phy3_host>;
  phy-names = "usb";
  power-domains = <&power 31>;
  status = "disabled";
 };

 usb_host2_xhci: usb@fcd00000 {
  compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
  reg = <0x0 0xfcd00000 0x0 0x400000>;
  interrupts = <0 222 4 0>;
  clocks = <&cru 362>, <&cru 361>,
    <&cru 360>, <&cru 363>,
    <&cru 370>;
  clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
  dr_mode = "host";
  phys = <&combphy2_psu 4>;
  phy-names = "usb3-phy";
  phy_type = "utmi_wide";
  resets = <&cru 308>;
  snps,dis_enblslpm_quirk;
  snps,dis-u2-freeclk-exists-quirk;
  snps,dis-del-phy-power-chg-quirk;
  snps,dis-tx-ipgap-linecheck-quirk;
  snps,dis_rxdet_inp3_quirk;
  status = "disabled";
 };

 sys_grf: syscon@fd58c000 {
  compatible = "rockchip,rk3588-sys-grf", "syscon";
  reg = <0x0 0xfd58c000 0x0 0x1000>;
 };

 bigcore0_grf: syscon@fd590000 {
  compatible = "rockchip,rk3588-bigcore0-grf", "syscon";
  reg = <0x0 0xfd590000 0x0 0x100>;
 };

 bigcore1_grf: syscon@fd592000 {
  compatible = "rockchip,rk3588-bigcore1-grf", "syscon";
  reg = <0x0 0xfd592000 0x0 0x100>;
 };

 php_grf: syscon@fd5b0000 {
  compatible = "rockchip,rk3588-php-grf", "syscon";
  reg = <0x0 0xfd5b0000 0x0 0x1000>;
 };

 pipe_phy0_grf: syscon@fd5bc000 {
  compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
  reg = <0x0 0xfd5bc000 0x0 0x100>;
 };

 pipe_phy2_grf: syscon@fd5c4000 {
  compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
  reg = <0x0 0xfd5c4000 0x0 0x100>;
 };

 usbdpphy0_grf: syscon@fd5c8000 {
  compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
  reg = <0x0 0xfd5c8000 0x0 0x4000>;
 };

 usb2phy0_grf: syscon@fd5d0000 {
  compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
        "simple-mfd";
  reg = <0x0 0xfd5d0000 0x0 0x4000>;
  #address-cells = <1>;
  #size-cells = <1>;

  u2phy0: usb2-phy@0 {
   compatible = "rockchip,rk3588-usb2phy";
   reg = <0x0 0x10>;
   interrupts = <0 393 4 0>;
   resets = <&cru 621>, <&cru 541>;
   reset-names = "phy", "apb";
   clocks = <&cru 672>;
   clock-names = "phyclk";
   clock-output-names = "usb480m_phy0";
   #clock-cells = <0>;
   status = "disabled";

   u2phy0_otg: otg-port {
    #phy-cells = <0>;
    status = "disabled";
   };
  };
 };

 usb2phy2_grf: syscon@fd5d8000 {
  compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
  reg = <0x0 0xfd5d8000 0x0 0x4000>;
  #address-cells = <1>;
  #size-cells = <1>;

  u2phy2: usb2-phy@8000 {
   compatible = "rockchip,rk3588-usb2phy";
   reg = <0x8000 0x10>;
   interrupts = <0 391 4 0>;
   resets = <&cru 623>, <&cru 543>;
   reset-names = "phy", "apb";
   clocks = <&cru 672>;
   clock-names = "phyclk";
   clock-output-names = "usb480m_phy2";
   #clock-cells = <0>;
   status = "disabled";

   u2phy2_host: host-port {
    #phy-cells = <0>;
    status = "disabled";
   };
  };
 };

 vo0_grf: syscon@fd5a6000 {
  compatible = "rockchip,rk3588-vo-grf", "syscon";
  reg = <0x0 0xfd5a6000 0x0 0x2000>;
  clocks = <&cru 489>;
 };

 usb_grf: syscon@fd5ac000 {
  compatible = "rockchip,rk3588-usb-grf", "syscon";
  reg = <0x0 0xfd5ac000 0x0 0x4000>;
 };

 usb2phy3_grf: syscon@fd5dc000 {
  compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
  reg = <0x0 0xfd5dc000 0x0 0x4000>;
  #address-cells = <1>;
  #size-cells = <1>;

  u2phy3: usb2-phy@c000 {
   compatible = "rockchip,rk3588-usb2phy";
   reg = <0xc000 0x10>;
   interrupts = <0 392 4 0>;
   resets = <&cru 624>, <&cru 544>;
   reset-names = "phy", "apb";
   clocks = <&cru 672>;
   clock-names = "phyclk";
   clock-output-names = "usb480m_phy3";
   #clock-cells = <0>;
   status = "disabled";

   u2phy3_host: host-port {
    #phy-cells = <0>;
    status = "disabled";
   };
  };
 };

 ioc: syscon@fd5f0000 {
  compatible = "rockchip,rk3588-ioc", "syscon";
  reg = <0x0 0xfd5f0000 0x0 0x10000>;
 };

 system_sram1: sram@fd600000 {
  compatible = "mmio-sram";
  reg = <0x0 0xfd600000 0x0 0x100000>;
  ranges = <0x0 0x0 0xfd600000 0x100000>;
  #address-cells = <1>;
  #size-cells = <1>;
 };

 cru: clock-controller@fd7c0000 {
  compatible = "rockchip,rk3588-cru";
  reg = <0x0 0xfd7c0000 0x0 0x5c000>;
  assigned-clocks =
   <&cru 8>, <&cru 4>,
   <&cru 7>, <&cru 6>,
   <&cru 204>,
   <&cru 206>, <&cru 205>,
   <&cru 256>, <&cru 257>,
   <&cru 258>, <&cru 646>,
   <&cru 647>, <&cru 605>,
   <&cru 113>, <&cru 224>,
   <&cru 262>;
  assigned-clock-rates =
   <1100000000>, <786432000>,
   <850000000>, <1188000000>,
   <702000000>,
   <400000000>, <500000000>,
   <800000000>, <100000000>,
   <400000000>, <100000000>,
   <200000000>, <500000000>,
   <375000000>, <150000000>,
   <200000000>;
  rockchip,grf = <&php_grf>;
  #clock-cells = <1>;
  #reset-cells = <1>;
 };

 i2c0: i2c@fd880000 {
  compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
  reg = <0x0 0xfd880000 0x0 0x1000>;
  interrupts = <0 317 4 0>;
  clocks = <&cru 628>, <&cru 627>;
  clock-names = "i2c", "pclk";
  pinctrl-0 = <&i2c0m0_xfer>;
  pinctrl-names = "default";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 uart0: serial@fd890000 {
  compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfd890000 0x0 0x100>;
  interrupts = <0 331 4 0>;
  clocks = <&cru 667>, <&cru 668>;
  clock-names = "baudclk", "apb_pclk";
  dmas = <&dmac0 6>, <&dmac0 7>;
  dma-names = "tx", "rx";
  pinctrl-0 = <&uart0m1_xfer>;
  pinctrl-names = "default";
  reg-shift = <2>;
  reg-io-width = <4>;
  status = "disabled";
 };

 pwm0: pwm@fd8b0000 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfd8b0000 0x0 0x10>;
  clocks = <&cru 658>, <&cru 657>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm0m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm1: pwm@fd8b0010 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfd8b0010 0x0 0x10>;
  clocks = <&cru 658>, <&cru 657>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm1m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm2: pwm@fd8b0020 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfd8b0020 0x0 0x10>;
  clocks = <&cru 658>, <&cru 657>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm2m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm3: pwm@fd8b0030 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfd8b0030 0x0 0x10>;
  clocks = <&cru 658>, <&cru 657>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm3m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pmu: power-management@fd8d8000 {
  compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
  reg = <0x0 0xfd8d8000 0x0 0x400>;

  power: power-controller {
   compatible = "rockchip,rk3588-power-controller";
   #address-cells = <1>;
   #power-domain-cells = <1>;
   #size-cells = <0>;
   status = "okay";


   power-domain@8 {
    reg = <8>;
    #power-domain-cells = <0>;
    #address-cells = <1>;
    #size-cells = <0>;

    power-domain@9 {
     reg = <9>;
     clocks = <&cru 289>,
       <&cru 291>,
       <&cru 290>,
       <&cru 280>;
     pm_qos = <&qos_npu0_mwr>,
       <&qos_npu0_mro>,
       <&qos_mcu_npu>;
     #power-domain-cells = <0>;
     #address-cells = <1>;
     #size-cells = <0>;

     power-domain@10 {
      reg = <10>;
      clocks = <&cru 289>,
        <&cru 291>,
        <&cru 290>;
      pm_qos = <&qos_npu1>;
      #power-domain-cells = <0>;
     };
     power-domain@11 {
      reg = <11>;
      clocks = <&cru 289>,
        <&cru 291>,
        <&cru 290>;
      pm_qos = <&qos_npu2>;
      #power-domain-cells = <0>;
     };
    };
   };

   power-domain@12 {
    reg = <12>;
    clocks = <&cru 262>,
      <&cru 263>,
      <&cru 264>;
    pm_qos = <&qos_gpu_m0>,
      <&qos_gpu_m1>,
      <&qos_gpu_m2>,
      <&qos_gpu_m3>;
    #power-domain-cells = <0>;
   };

   power-domain@13 {
    reg = <13>;
    #address-cells = <1>;
    #size-cells = <0>;
    #power-domain-cells = <0>;

    power-domain@14 {
     reg = <14>;
     clocks = <&cru 384>,
       <&cru 431>,
       <&cru 429>,
       <&cru 385>,
       <&cru 383>;
     pm_qos = <&qos_rkvdec0>;
     #power-domain-cells = <0>;
    };
    power-domain@15 {
     reg = <15>;
     clocks = <&cru 389>,
       <&cru 431>,
       <&cru 429>,
       <&cru 390>;
     pm_qos = <&qos_rkvdec1>;
     #power-domain-cells = <0>;
    };
    power-domain@16 {
     reg = <16>;
     clocks = <&cru 437>,
       <&cru 438>;
     pm_qos = <&qos_rkvenc0_m0ro>,
       <&qos_rkvenc0_m1ro>,
       <&qos_rkvenc0_m2wo>;
     #address-cells = <1>;
     #size-cells = <0>;
     #power-domain-cells = <0>;

     power-domain@17 {
      reg = <17>;
      clocks = <&cru 442>,
        <&cru 437>,
        <&cru 438>,
        <&cru 443>;
      pm_qos = <&qos_rkvenc1_m0ro>,
        <&qos_rkvenc1_m1ro>,
        <&qos_rkvenc1_m2wo>;
      #power-domain-cells = <0>;
     };
    };
   };

   power-domain@21 {
    reg = <21>;
    clocks = <&cru 431>,
      <&cru 430>,
      <&cru 429>,
      <&cru 432>,
      <&cru 411>,
      <&cru 410>,
      <&cru 413>,
      <&cru 414>,
      <&cru 415>,
      <&cru 416>,
      <&cru 417>,
      <&cru 418>,
      <&cru 419>,
      <&cru 420>,
      <&cru 421>,
      <&cru 422>,
      <&cru 424>,
      <&cru 423>;
    pm_qos = <&qos_iep>,
      <&qos_jpeg_dec>,
      <&qos_jpeg_enc0>,
      <&qos_jpeg_enc1>,
      <&qos_jpeg_enc2>,
      <&qos_jpeg_enc3>,
      <&qos_rga2_mro>,
      <&qos_rga2_mwo>;
    #address-cells = <1>;
    #size-cells = <0>;
    #power-domain-cells = <0>;


    power-domain@23 {
     reg = <23>;
     clocks = <&cru 67>,
       <&cru 65>,
       <&cru 431>;
     pm_qos = <&qos_av1>;
     #power-domain-cells = <0>;
    };
    power-domain@14 {
     reg = <14>;
     clocks = <&cru 384>,
       <&cru 431>,
       <&cru 429>,
       <&cru 385>;
     pm_qos = <&qos_rkvdec0>;
     #power-domain-cells = <0>;
    };
    power-domain@15 {
     reg = <15>;
     clocks = <&cru 389>,
       <&cru 431>,
       <&cru 429>;
     pm_qos = <&qos_rkvdec1>;
     #power-domain-cells = <0>;
    };
    power-domain@22 {
     reg = <22>;
     clocks = <&cru 427>,
       <&cru 426>;
     pm_qos = <&qos_rga3_0>;
     #power-domain-cells = <0>;
    };
   };
   power-domain@24 {
    reg = <24>;
    clocks = <&cru 603>,
      <&cru 602>,
      <&cru 605>;
    pm_qos = <&qos_vop_m0>,
      <&qos_vop_m1>;
    #address-cells = <1>;
    #size-cells = <0>;
    #power-domain-cells = <0>;

    power-domain@25 {
     reg = <25>;
     clocks = <&cru 487>,
       <&cru 488>,
       <&cru 486>,
       <&cru 484>,
       <&cru 479>,
       <&cru 478>,
       <&cru 602>;
     pm_qos = <&qos_hdcp0>;
     #power-domain-cells = <0>;
    };
   };
   power-domain@26 {
    reg = <26>;
    clocks = <&cru 541>,
      <&cru 542>,
      <&cru 540>,
      <&cru 519>,
      <&cru 518>,
      <&cru 538>,
      <&cru 593>;
    pm_qos = <&qos_hdcp1>,
      <&qos_hdmirx>;
    #power-domain-cells = <0>;
   };
   power-domain@27 {
    reg = <27>;
    clocks = <&cru 466>,
      <&cru 467>,
      <&cru 464>,
      <&cru 463>,
      <&cru 470>,
      <&cru 469>;
    pm_qos = <&qos_isp0_mro>,
      <&qos_isp0_mwo>,
      <&qos_vicap_m0>,
      <&qos_vicap_m1>;
    #address-cells = <1>;
    #size-cells = <0>;
    #power-domain-cells = <0>;

    power-domain@28 {
     reg = <28>;
     clocks = <&cru 275>,
       <&cru 274>,
       <&cru 466>,
       <&cru 467>;
     pm_qos = <&qos_isp1_mwo>,
       <&qos_isp1_mro>;
     #power-domain-cells = <0>;
    };
    power-domain@29 {
     reg = <29>;
     clocks = <&cru 455>,
       <&cru 454>,
       <&cru 458>,
       <&cru 457>,
       <&cru 467>;
     pm_qos = <&qos_fisheye0>,
       <&qos_fisheye1>;
     #power-domain-cells = <0>;
    };
   };
   power-domain@30 {
    reg = <30>;
    clocks = <&cru 378>,
      <&cru 379>;
    pm_qos = <&qos_rga3_1>;
    #power-domain-cells = <0>;
   };
   power-domain@31 {
    reg = <31>;
    clocks = <&cru 343>,
      <&cru 396>,
      <&cru 397>,
      <&cru 398>,
      <&cru 399>,
      <&cru 400>,
      <&cru 401>;
    pm_qos = <&qos_usb3_0>,
      <&qos_usb3_1>,
      <&qos_usb2host_0>,
      <&qos_usb2host_1>;
    #power-domain-cells = <0>;
   };
   power-domain@33 {
    reg = <33>;
    clocks = <&cru 343>,
      <&cru 346>,
      <&cru 347>;
    #power-domain-cells = <0>;
   };
   power-domain@34 {
    reg = <34>;
    clocks = <&cru 343>,
      <&cru 346>,
      <&cru 347>;
    #power-domain-cells = <0>;
   };
   power-domain@37 {
    reg = <37>;
    clocks = <&cru 394>,
      <&cru 306>;
    pm_qos = <&qos_sdio>;
    #power-domain-cells = <0>;
   };
   power-domain@38 {
    reg = <38>;
    clocks = <&cru 52>,
      <&cru 53>;
    #power-domain-cells = <0>;
   };
   power-domain@40 {
    reg = <40>;
    pm_qos = <&qos_sdmmc>;
    #power-domain-cells = <0>;
   };
  };
 };

 i2s4_8ch: i2s@fddc0000 {
  compatible = "rockchip,rk3588-i2s-tdm";
  reg = <0x0 0xfddc0000 0x0 0x1000>;
  interrupts = <0 184 4 0>;
  clocks = <&cru 492>, <&cru 492>, <&cru 481>;
  clock-names = "mclk_tx", "mclk_rx", "hclk";
  assigned-clocks = <&cru 490>;
  assigned-clock-parents = <&cru 4>;
  dmas = <&dmac2 0>;
  dma-names = "tx";
  power-domains = <&power 25>;
  resets = <&cru 440>;
  reset-names = "tx-m";
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 i2s5_8ch: i2s@fddf0000 {
  compatible = "rockchip,rk3588-i2s-tdm";
  reg = <0x0 0xfddf0000 0x0 0x1000>;
  interrupts = <0 185 4 0>;
  clocks = <&cru 564>, <&cru 564>, <&cru 565>;
  clock-names = "mclk_tx", "mclk_rx", "hclk";
  assigned-clocks = <&cru 561>;
  assigned-clock-parents = <&cru 4>;
  dmas = <&dmac2 2>;
  dma-names = "tx";
  power-domains = <&power 26>;
  resets = <&cru 472>;
  reset-names = "tx-m";
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 i2s9_8ch: i2s@fddfc000 {
  compatible = "rockchip,rk3588-i2s-tdm";
  reg = <0x0 0xfddfc000 0x0 0x1000>;
  interrupts = <0 189 4 0>;
  clocks = <&cru 560>, <&cru 560>, <&cru 556>;
  clock-names = "mclk_tx", "mclk_rx", "hclk";
  assigned-clocks = <&cru 557>;
  assigned-clock-parents = <&cru 4>;
  dmas = <&dmac2 23>;
  dma-names = "rx";
  power-domains = <&power 26>;
  resets = <&cru 492>;
  reset-names = "rx-m";
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 qos_gpu_m0: qos@fdf35000 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf35000 0x0 0x20>;
 };

 qos_gpu_m1: qos@fdf35200 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf35200 0x0 0x20>;
 };

 qos_gpu_m2: qos@fdf35400 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf35400 0x0 0x20>;
 };

 qos_gpu_m3: qos@fdf35600 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf35600 0x0 0x20>;
 };

 qos_rga3_1: qos@fdf36000 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf36000 0x0 0x20>;
 };

 qos_sdio: qos@fdf39000 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf39000 0x0 0x20>;
 };

 qos_sdmmc: qos@fdf3d800 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf3d800 0x0 0x20>;
 };

 qos_usb3_1: qos@fdf3e000 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf3e000 0x0 0x20>;
 };

 qos_usb3_0: qos@fdf3e200 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf3e200 0x0 0x20>;
 };

 qos_usb2host_0: qos@fdf3e400 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf3e400 0x0 0x20>;
 };

 qos_usb2host_1: qos@fdf3e600 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf3e600 0x0 0x20>;
 };

 qos_fisheye0: qos@fdf40000 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf40000 0x0 0x20>;
 };

 qos_fisheye1: qos@fdf40200 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf40200 0x0 0x20>;
 };

 qos_isp0_mro: qos@fdf40400 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf40400 0x0 0x20>;
 };

 qos_isp0_mwo: qos@fdf40500 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf40500 0x0 0x20>;
 };

 qos_vicap_m0: qos@fdf40600 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf40600 0x0 0x20>;
 };

 qos_vicap_m1: qos@fdf40800 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf40800 0x0 0x20>;
 };

 qos_isp1_mwo: qos@fdf41000 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf41000 0x0 0x20>;
 };

 qos_isp1_mro: qos@fdf41100 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf41100 0x0 0x20>;
 };

 qos_rkvenc0_m0ro: qos@fdf60000 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf60000 0x0 0x20>;
 };

 qos_rkvenc0_m1ro: qos@fdf60200 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf60200 0x0 0x20>;
 };

 qos_rkvenc0_m2wo: qos@fdf60400 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf60400 0x0 0x20>;
 };

 qos_rkvenc1_m0ro: qos@fdf61000 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf61000 0x0 0x20>;
 };

 qos_rkvenc1_m1ro: qos@fdf61200 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf61200 0x0 0x20>;
 };

 qos_rkvenc1_m2wo: qos@fdf61400 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf61400 0x0 0x20>;
 };

 qos_rkvdec0: qos@fdf62000 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf62000 0x0 0x20>;
 };

 qos_rkvdec1: qos@fdf63000 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf63000 0x0 0x20>;
 };

 qos_av1: qos@fdf64000 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf64000 0x0 0x20>;
 };

 qos_iep: qos@fdf66000 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf66000 0x0 0x20>;
 };

 qos_jpeg_dec: qos@fdf66200 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf66200 0x0 0x20>;
 };

 qos_jpeg_enc0: qos@fdf66400 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf66400 0x0 0x20>;
 };

 qos_jpeg_enc1: qos@fdf66600 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf66600 0x0 0x20>;
 };

 qos_jpeg_enc2: qos@fdf66800 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf66800 0x0 0x20>;
 };

 qos_jpeg_enc3: qos@fdf66a00 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf66a00 0x0 0x20>;
 };

 qos_rga2_mro: qos@fdf66c00 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf66c00 0x0 0x20>;
 };

 qos_rga2_mwo: qos@fdf66e00 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf66e00 0x0 0x20>;
 };

 qos_rga3_0: qos@fdf67000 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf67000 0x0 0x20>;
 };

 qos_vdpu: qos@fdf67200 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf67200 0x0 0x20>;
 };

 qos_npu1: qos@fdf70000 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf70000 0x0 0x20>;
 };

 qos_npu2: qos@fdf71000 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf71000 0x0 0x20>;
 };

 qos_npu0_mwr: qos@fdf72000 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf72000 0x0 0x20>;
 };

 qos_npu0_mro: qos@fdf72200 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf72200 0x0 0x20>;
 };

 qos_mcu_npu: qos@fdf72400 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf72400 0x0 0x20>;
 };

 qos_hdcp0: qos@fdf80000 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf80000 0x0 0x20>;
 };

 qos_hdcp1: qos@fdf81000 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf81000 0x0 0x20>;
 };

 qos_hdmirx: qos@fdf81200 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf81200 0x0 0x20>;
 };

 qos_vop_m0: qos@fdf82000 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf82000 0x0 0x20>;
 };

 qos_vop_m1: qos@fdf82200 {
  compatible = "rockchip,rk3588-qos", "syscon";
  reg = <0x0 0xfdf82200 0x0 0x20>;
 };

 pcie2x1l1: pcie@fe180000 {
  compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
  bus-range = <0x30 0x3f>;
  clocks = <&cru 323>, <&cru 328>,
    <&cru 318>, <&cru 333>,
    <&cru 338>, <&cru 688>;
  clock-names = "aclk_mst", "aclk_slv",
         "aclk_dbi", "pclk",
         "aux", "pipe";
  device_type = "pci";
  interrupts = <0 248 4 0>,
        <0 247 4 0>,
        <0 246 4 0>,
        <0 245 4 0>,
        <0 244 4 0>;
  interrupt-names = "sys", "pmc", "msg", "legacy", "err";
  #interrupt-cells = <1>;
  interrupt-map-mask = <0 0 0 7>;
  interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
    <0 0 0 2 &pcie2x1l1_intc 1>,
    <0 0 0 3 &pcie2x1l1_intc 2>,
    <0 0 0 4 &pcie2x1l1_intc 3>;
  linux,pci-domain = <3>;
  max-link-speed = <2>;
  msi-map = <0x3000 &its0 0x3000 0x1000>;
  num-lanes = <1>;
  phys = <&combphy2_psu 2>;
  phy-names = "pcie-phy";
  power-domains = <&power 34>;
  ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
    <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
    <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
  reg = <0xa 0x40c00000 0x0 0x00400000>,
        <0x0 0xfe180000 0x0 0x00010000>,
        <0x0 0xf3000000 0x0 0x00100000>;
  reg-names = "dbi", "apb", "config";
  resets = <&cru 297>, <&cru 302>;
  reset-names = "pwr", "pipe";
  #address-cells = <3>;
  #size-cells = <2>;
  status = "disabled";

  pcie2x1l1_intc: legacy-interrupt-controller {
   interrupt-controller;
   #address-cells = <0>;
   #interrupt-cells = <1>;
   interrupt-parent = <&gic>;
   interrupts = <0 245 1 0>;
  };
 };

 pcie2x1l2: pcie@fe190000 {
  compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
  bus-range = <0x40 0x4f>;
  clocks = <&cru 324>, <&cru 329>,
    <&cru 319>, <&cru 334>,
    <&cru 339>, <&cru 371>;
  clock-names = "aclk_mst", "aclk_slv",
         "aclk_dbi", "pclk",
         "aux", "pipe";
  device_type = "pci";
  interrupts = <0 253 4 0>,
        <0 252 4 0>,
        <0 251 4 0>,
        <0 250 4 0>,
        <0 249 4 0>;
  interrupt-names = "sys", "pmc", "msg", "legacy", "err";
  #interrupt-cells = <1>;
  interrupt-map-mask = <0 0 0 7>;
  interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
    <0 0 0 2 &pcie2x1l2_intc 1>,
    <0 0 0 3 &pcie2x1l2_intc 2>,
    <0 0 0 4 &pcie2x1l2_intc 3>;
  linux,pci-domain = <4>;
  max-link-speed = <2>;
  msi-map = <0x4000 &its0 0x4000 0x1000>;
  num-lanes = <1>;
  phys = <&combphy0_ps 2>;
  phy-names = "pcie-phy";
  power-domains = <&power 34>;
  ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
    <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
    <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
  reg = <0xa 0x41000000 0x0 0x00400000>,
        <0x0 0xfe190000 0x0 0x00010000>,
        <0x0 0xf4000000 0x0 0x00100000>;
  reg-names = "dbi", "apb", "config";
  resets = <&cru 298>, <&cru 303>;
  reset-names = "pwr", "pipe";
  #address-cells = <3>;
  #size-cells = <2>;
  status = "disabled";

  pcie2x1l2_intc: legacy-interrupt-controller {
   interrupt-controller;
   #address-cells = <0>;
   #interrupt-cells = <1>;
   interrupt-parent = <&gic>;
   interrupts = <0 250 1 0>;
  };
 };

 gmac1: ethernet@fe1c0000 {
  compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
  reg = <0x0 0xfe1c0000 0x0 0x10000>;
  interrupts = <0 234 4 0>,
        <0 233 4 0>;
  interrupt-names = "macirq", "eth_wake_irq";
  clocks = <&cru 310>, <&cru 311>,
    <&cru 345>, <&cru 350>,
    <&cru 309>;
  clock-names = "stmmaceth", "clk_mac_ref",
         "pclk_mac", "aclk_mac",
         "ptp_ref";
  power-domains = <&power 33>;
  resets = <&cru 292>;
  reset-names = "stmmaceth";
  rockchip,grf = <&sys_grf>;
  rockchip,php-grf = <&php_grf>;
  snps,axi-config = <&gmac1_stmmac_axi_setup>;
  snps,mixed-burst;
  snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
  snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
  snps,tso;
  status = "disabled";

  mdio1: mdio {
   compatible = "snps,dwmac-mdio";
   #address-cells = <0x1>;
   #size-cells = <0x0>;
  };

  gmac1_stmmac_axi_setup: stmmac-axi-config {
   snps,blen = <0 0 0 0 16 8 4>;
   snps,wr_osr_lmt = <4>;
   snps,rd_osr_lmt = <8>;
  };

  gmac1_mtl_rx_setup: rx-queues-config {
   snps,rx-queues-to-use = <2>;
   queue0 {};
   queue1 {};
  };

  gmac1_mtl_tx_setup: tx-queues-config {
   snps,tx-queues-to-use = <2>;
   queue0 {};
   queue1 {};
  };
 };

 sata0: sata@fe210000 {
  compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
  reg = <0 0xfe210000 0 0x1000>;
  interrupts = <0 273 4 0>;
  clocks = <&cru 354>, <&cru 351>,
    <&cru 357>, <&cru 340>,
    <&cru 367>;
  clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
  ports-implemented = <0x1>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";

  sata-port@0 {
   reg = <0>;
   hba-port-cap = <(1 << 22)>;
   phys = <&combphy0_ps 1>;
   phy-names = "sata-phy";
   snps,rx-ts-max = <32>;
   snps,tx-ts-max = <32>;
  };
 };

 sata2: sata@fe230000 {
  compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
  reg = <0 0xfe230000 0 0x1000>;
  interrupts = <0 275 4 0>;
  clocks = <&cru 356>, <&cru 353>,
    <&cru 359>, <&cru 342>,
    <&cru 369>;
  clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
  ports-implemented = <0x1>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";

  sata-port@0 {
   reg = <0>;
   hba-port-cap = <(1 << 22)>;
   phys = <&combphy2_psu 1>;
   phy-names = "sata-phy";
   snps,rx-ts-max = <32>;
   snps,tx-ts-max = <32>;
  };
 };

 sfc: spi@fe2b0000 {
  compatible = "rockchip,sfc";
  reg = <0x0 0xfe2b0000 0x0 0x4000>;
  interrupts = <0 206 4 0>;
  clocks = <&cru 303>, <&cru 304>;
  clock-names = "clk_sfc", "hclk_sfc";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 sdmmc: mmc@fe2c0000 {
  compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
  reg = <0x0 0xfe2c0000 0x0 0x4000>;
  interrupts = <0 203 4 0>;
  clocks = <&scmi_clk 23>, <&scmi_clk 9>,
    <&cru 685>, <&cru 686>;
  clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  fifo-depth = <0x100>;
  max-frequency = <200000000>;
  pinctrl-names = "default";
  pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
  power-domains = <&power 40>;
  status = "disabled";
 };

 sdio: mmc@fe2d0000 {
  compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
  reg = <0x00 0xfe2d0000 0x00 0x4000>;
  interrupts = <0 204 4 0>;
  clocks = <&cru 394>, <&cru 395>,
    <&cru 683>, <&cru 684>;
  clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  fifo-depth = <0x100>;
  max-frequency = <200000000>;
  pinctrl-names = "default";
  pinctrl-0 = <&sdiom1_pins>;
  power-domains = <&power 37>;
  status = "disabled";
 };

 sdhci: mmc@fe2e0000 {
  compatible = "rockchip,rk3588-dwcmshc";
  reg = <0x0 0xfe2e0000 0x0 0x10000>;
  interrupts = <0 205 4 0>;
  assigned-clocks = <&cru 301>, <&cru 302>, <&cru 300>;
  assigned-clock-rates = <200000000>, <24000000>, <200000000>;
  clocks = <&cru 300>, <&cru 298>,
    <&cru 299>, <&cru 301>,
    <&cru 302>;
  clock-names = "core", "bus", "axi", "block", "timer";
  max-frequency = <200000000>;
  pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
       <&emmc_cmd>, <&emmc_data_strobe>;
  pinctrl-names = "default";
  resets = <&cru 280>, <&cru 278>,
    <&cru 279>, <&cru 281>,
    <&cru 282>;
  reset-names = "core", "bus", "axi", "block", "timer";
  status = "disabled";
 };

 i2s0_8ch: i2s@fe470000 {
  compatible = "rockchip,rk3588-i2s-tdm";
  reg = <0x0 0xfe470000 0x0 0x1000>;
  interrupts = <0 180 4 0>;
  clocks = <&cru 43>, <&cru 47>, <&cru 40>;
  clock-names = "mclk_tx", "mclk_rx", "hclk";
  assigned-clocks = <&cru 41>, <&cru 45>;
  assigned-clock-parents = <&cru 4>, <&cru 4>;
  dmas = <&dmac0 0>, <&dmac0 1>;
  dma-names = "tx", "rx";
  power-domains = <&power 38>;
  resets = <&cru 42>, <&cru 43>;
  reset-names = "tx-m", "rx-m";
  rockchip,trcm-sync-tx-only;
  pinctrl-names = "default";
  pinctrl-0 = <&i2s0_lrck
        &i2s0_sclk
        &i2s0_sdi0
        &i2s0_sdi1
        &i2s0_sdi2
        &i2s0_sdi3
        &i2s0_sdo0
        &i2s0_sdo1
        &i2s0_sdo2
        &i2s0_sdo3>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 i2s1_8ch: i2s@fe480000 {
  compatible = "rockchip,rk3588-i2s-tdm";
  reg = <0x0 0xfe480000 0x0 0x1000>;
  interrupts = <0 181 4 0>;
  clocks = <&cru 633>, <&cru 637>, <&cru 629>;
  clock-names = "mclk_tx", "mclk_rx", "hclk";
  dmas = <&dmac0 2>, <&dmac0 3>;
  dma-names = "tx", "rx";
  resets = <&cru 606>, <&cru 607>;
  reset-names = "tx-m", "rx-m";
  rockchip,trcm-sync-tx-only;
  pinctrl-names = "default";
  pinctrl-0 = <&i2s1m0_lrck
        &i2s1m0_sclk
        &i2s1m0_sdi0
        &i2s1m0_sdi1
        &i2s1m0_sdi2
        &i2s1m0_sdi3
        &i2s1m0_sdo0
        &i2s1m0_sdo1
        &i2s1m0_sdo2
        &i2s1m0_sdo3>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 i2s2_2ch: i2s@fe490000 {
  compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
  reg = <0x0 0xfe490000 0x0 0x1000>;
  interrupts = <0 182 4 0>;
  clocks = <&cru 31>, <&cru 26>;
  clock-names = "i2s_clk", "i2s_hclk";
  assigned-clocks = <&cru 28>;
  assigned-clock-parents = <&cru 4>;
  dmas = <&dmac1 0>, <&dmac1 1>;
  dma-names = "tx", "rx";
  power-domains = <&power 38>;
  rockchip,trcm-sync-tx-only;
  pinctrl-names = "default";
  pinctrl-0 = <&i2s2m1_lrck
        &i2s2m1_sclk
        &i2s2m1_sdi
        &i2s2m1_sdo>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 i2s3_2ch: i2s@fe4a0000 {
  compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
  reg = <0x0 0xfe4a0000 0x0 0x1000>;
  interrupts = <0 183 4 0>;
  clocks = <&cru 37>, <&cru 27>;
  clock-names = "i2s_clk", "i2s_hclk";
  assigned-clocks = <&cru 34>;
  assigned-clock-parents = <&cru 4>;
  dmas = <&dmac1 2>, <&dmac1 3>;
  dma-names = "tx", "rx";
  power-domains = <&power 38>;
  rockchip,trcm-sync-tx-only;
  pinctrl-names = "default";
  pinctrl-0 = <&i2s3_lrck
        &i2s3_sclk
        &i2s3_sdi
        &i2s3_sdo>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 gic: interrupt-controller@fe600000 {
  compatible = "arm,gic-v3";
  reg = <0x0 0xfe600000 0 0x10000>,
        <0x0 0xfe680000 0 0x100000>;
  interrupts = <1 9 4 0>;
  interrupt-controller;
  mbi-alias = <0x0 0xfe610000>;
  mbi-ranges = <424 56>;
  msi-controller;
  ranges;
  #address-cells = <2>;
  #interrupt-cells = <4>;
  #size-cells = <2>;

  its0: msi-controller@fe640000 {
   compatible = "arm,gic-v3-its";
   reg = <0x0 0xfe640000 0x0 0x20000>;
   msi-controller;
   #msi-cells = <1>;
  };

  its1: msi-controller@fe660000 {
   compatible = "arm,gic-v3-its";
   reg = <0x0 0xfe660000 0x0 0x20000>;
   msi-controller;
   #msi-cells = <1>;
  };

  ppi-partitions {
   ppi_partition0: interrupt-partition-0 {
    affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
   };

   ppi_partition1: interrupt-partition-1 {
    affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>;
   };
  };
 };

 dmac0: dma-controller@fea10000 {
  compatible = "arm,pl330", "arm,primecell";
  reg = <0x0 0xfea10000 0x0 0x4000>;
  interrupts = <0 86 4 0>,
        <0 87 4 0>;
  arm,pl330-periph-burst;
  clocks = <&cru 110>;
  clock-names = "apb_pclk";
  #dma-cells = <1>;
 };

 dmac1: dma-controller@fea30000 {
  compatible = "arm,pl330", "arm,primecell";
  reg = <0x0 0xfea30000 0x0 0x4000>;
  interrupts = <0 88 4 0>,
        <0 89 4 0>;
  arm,pl330-periph-burst;
  clocks = <&cru 111>;
  clock-names = "apb_pclk";
  #dma-cells = <1>;
 };

 i2c1: i2c@fea90000 {
  compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
  reg = <0x0 0xfea90000 0x0 0x1000>;
  clocks = <&cru 131>, <&cru 123>;
  clock-names = "i2c", "pclk";
  interrupts = <0 318 4 0>;
  pinctrl-0 = <&i2c1m0_xfer>;
  pinctrl-names = "default";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c2: i2c@feaa0000 {
  compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
  reg = <0x0 0xfeaa0000 0x0 0x1000>;
  clocks = <&cru 132>, <&cru 124>;
  clock-names = "i2c", "pclk";
  interrupts = <0 319 4 0>;
  pinctrl-0 = <&i2c2m0_xfer>;
  pinctrl-names = "default";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c3: i2c@feab0000 {
  compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
  reg = <0x0 0xfeab0000 0x0 0x1000>;
  clocks = <&cru 133>, <&cru 125>;
  clock-names = "i2c", "pclk";
  interrupts = <0 320 4 0>;
  pinctrl-0 = <&i2c3m0_xfer>;
  pinctrl-names = "default";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c4: i2c@feac0000 {
  compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
  reg = <0x0 0xfeac0000 0x0 0x1000>;
  clocks = <&cru 134>, <&cru 126>;
  clock-names = "i2c", "pclk";
  interrupts = <0 321 4 0>;
  pinctrl-0 = <&i2c4m0_xfer>;
  pinctrl-names = "default";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c5: i2c@fead0000 {
  compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
  reg = <0x0 0xfead0000 0x0 0x1000>;
  clocks = <&cru 135>, <&cru 127>;
  clock-names = "i2c", "pclk";
  interrupts = <0 322 4 0>;
  pinctrl-0 = <&i2c5m0_xfer>;
  pinctrl-names = "default";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 timer0: timer@feae0000 {
  compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
  reg = <0x0 0xfeae0000 0x0 0x20>;
  interrupts = <0 289 4 0>;
  clocks = <&cru 84>, <&cru 87>;
  clock-names = "pclk", "timer";
 };

 wdt: watchdog@feaf0000 {
  compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
  reg = <0x0 0xfeaf0000 0x0 0x100>;
  clocks = <&cru 100>, <&cru 99>;
  clock-names = "tclk", "pclk";
  interrupts = <0 315 4 0>;
 };

 spi0: spi@feb00000 {
  compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
  reg = <0x0 0xfeb00000 0x0 0x1000>;
  interrupts = <0 326 4 0>;
  clocks = <&cru 151>, <&cru 146>;
  clock-names = "spiclk", "apb_pclk";
  dmas = <&dmac0 14>, <&dmac0 15>;
  dma-names = "tx", "rx";
  num-cs = <2>;
  pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
  pinctrl-names = "default";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 spi1: spi@feb10000 {
  compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
  reg = <0x0 0xfeb10000 0x0 0x1000>;
  interrupts = <0 327 4 0>;
  clocks = <&cru 152>, <&cru 147>;
  clock-names = "spiclk", "apb_pclk";
  dmas = <&dmac0 16>, <&dmac0 17>;
  dma-names = "tx", "rx";
  num-cs = <2>;
  pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
  pinctrl-names = "default";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 spi2: spi@feb20000 {
  compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
  reg = <0x0 0xfeb20000 0x0 0x1000>;
  interrupts = <0 328 4 0>;
  clocks = <&cru 153>, <&cru 148>;
  clock-names = "spiclk", "apb_pclk";
  dmas = <&dmac1 15>, <&dmac1 16>;
  dma-names = "tx", "rx";
  num-cs = <2>;
  pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
  pinctrl-names = "default";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 spi3: spi@feb30000 {
  compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
  reg = <0x0 0xfeb30000 0x0 0x1000>;
  interrupts = <0 329 4 0>;
  clocks = <&cru 154>, <&cru 149>;
  clock-names = "spiclk", "apb_pclk";
  dmas = <&dmac1 17>, <&dmac1 18>;
  dma-names = "tx", "rx";
  num-cs = <2>;
  pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
  pinctrl-names = "default";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 uart1: serial@feb40000 {
  compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfeb40000 0x0 0x100>;
  interrupts = <0 332 4 0>;
  clocks = <&cru 171>, <&cru 159>;
  clock-names = "baudclk", "apb_pclk";
  dmas = <&dmac0 8>, <&dmac0 9>;
  dma-names = "tx", "rx";
  pinctrl-0 = <&uart1m1_xfer>;
  pinctrl-names = "default";
  reg-io-width = <4>;
  reg-shift = <2>;
  status = "disabled";
 };

 uart2: serial@feb50000 {
  compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfeb50000 0x0 0x100>;
  interrupts = <0 333 4 0>;
  clocks = <&cru 175>, <&cru 160>;
  clock-names = "baudclk", "apb_pclk";
  dmas = <&dmac0 10>, <&dmac0 11>;
  dma-names = "tx", "rx";
  pinctrl-0 = <&uart2m1_xfer>;
  pinctrl-names = "default";
  reg-io-width = <4>;
  reg-shift = <2>;
  status = "disabled";
 };

 uart3: serial@feb60000 {
  compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfeb60000 0x0 0x100>;
  interrupts = <0 334 4 0>;
  clocks = <&cru 179>, <&cru 161>;
  clock-names = "baudclk", "apb_pclk";
  dmas = <&dmac0 12>, <&dmac0 13>;
  dma-names = "tx", "rx";
  pinctrl-0 = <&uart3m1_xfer>;
  pinctrl-names = "default";
  reg-io-width = <4>;
  reg-shift = <2>;
  status = "disabled";
 };

 uart4: serial@feb70000 {
  compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfeb70000 0x0 0x100>;
  interrupts = <0 335 4 0>;
  clocks = <&cru 183>, <&cru 162>;
  clock-names = "baudclk", "apb_pclk";
  dmas = <&dmac1 9>, <&dmac1 10>;
  dma-names = "tx", "rx";
  pinctrl-0 = <&uart4m1_xfer>;
  pinctrl-names = "default";
  reg-io-width = <4>;
  reg-shift = <2>;
  status = "disabled";
 };

 uart5: serial@feb80000 {
  compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfeb80000 0x0 0x100>;
  interrupts = <0 336 4 0>;
  clocks = <&cru 187>, <&cru 163>;
  clock-names = "baudclk", "apb_pclk";
  dmas = <&dmac1 11>, <&dmac1 12>;
  dma-names = "tx", "rx";
  pinctrl-0 = <&uart5m1_xfer>;
  pinctrl-names = "default";
  reg-io-width = <4>;
  reg-shift = <2>;
  status = "disabled";
 };

 uart6: serial@feb90000 {
  compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfeb90000 0x0 0x100>;
  interrupts = <0 337 4 0>;
  clocks = <&cru 191>, <&cru 164>;
  clock-names = "baudclk", "apb_pclk";
  dmas = <&dmac1 13>, <&dmac1 14>;
  dma-names = "tx", "rx";
  pinctrl-0 = <&uart6m1_xfer>;
  pinctrl-names = "default";
  reg-io-width = <4>;
  reg-shift = <2>;
  status = "disabled";
 };

 uart7: serial@feba0000 {
  compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfeba0000 0x0 0x100>;
  interrupts = <0 338 4 0>;
  clocks = <&cru 195>, <&cru 165>;
  clock-names = "baudclk", "apb_pclk";
  dmas = <&dmac2 7>, <&dmac2 8>;
  dma-names = "tx", "rx";
  pinctrl-0 = <&uart7m1_xfer>;
  pinctrl-names = "default";
  reg-io-width = <4>;
  reg-shift = <2>;
  status = "disabled";
 };

 uart8: serial@febb0000 {
  compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfebb0000 0x0 0x100>;
  interrupts = <0 339 4 0>;
  clocks = <&cru 199>, <&cru 166>;
  clock-names = "baudclk", "apb_pclk";
  dmas = <&dmac2 9>, <&dmac2 10>;
  dma-names = "tx", "rx";
  pinctrl-0 = <&uart8m1_xfer>;
  pinctrl-names = "default";
  reg-io-width = <4>;
  reg-shift = <2>;
  status = "disabled";
 };

 uart9: serial@febc0000 {
  compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfebc0000 0x0 0x100>;
  interrupts = <0 340 4 0>;
  clocks = <&cru 203>, <&cru 167>;
  clock-names = "baudclk", "apb_pclk";
  dmas = <&dmac2 11>, <&dmac2 12>;
  dma-names = "tx", "rx";
  pinctrl-0 = <&uart9m1_xfer>;
  pinctrl-names = "default";
  reg-io-width = <4>;
  reg-shift = <2>;
  status = "disabled";
 };

 pwm4: pwm@febd0000 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfebd0000 0x0 0x10>;
  clocks = <&cru 76>, <&cru 75>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm4m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm5: pwm@febd0010 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfebd0010 0x0 0x10>;
  clocks = <&cru 76>, <&cru 75>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm5m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm6: pwm@febd0020 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfebd0020 0x0 0x10>;
  clocks = <&cru 76>, <&cru 75>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm6m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm7: pwm@febd0030 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfebd0030 0x0 0x10>;
  clocks = <&cru 76>, <&cru 75>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm7m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm8: pwm@febe0000 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfebe0000 0x0 0x10>;
  clocks = <&cru 79>, <&cru 78>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm8m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm9: pwm@febe0010 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfebe0010 0x0 0x10>;
  clocks = <&cru 79>, <&cru 78>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm9m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm10: pwm@febe0020 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfebe0020 0x0 0x10>;
  clocks = <&cru 79>, <&cru 78>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm10m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm11: pwm@febe0030 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfebe0030 0x0 0x10>;
  clocks = <&cru 79>, <&cru 78>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm11m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm12: pwm@febf0000 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfebf0000 0x0 0x10>;
  clocks = <&cru 82>, <&cru 81>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm12m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm13: pwm@febf0010 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfebf0010 0x0 0x10>;
  clocks = <&cru 82>, <&cru 81>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm13m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm14: pwm@febf0020 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfebf0020 0x0 0x10>;
  clocks = <&cru 82>, <&cru 81>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm14m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm15: pwm@febf0030 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfebf0030 0x0 0x10>;
  clocks = <&cru 82>, <&cru 81>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm15m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 tsadc: tsadc@fec00000 {
  compatible = "rockchip,rk3588-tsadc";
  reg = <0x0 0xfec00000 0x0 0x400>;
  interrupts = <0 397 4 0>;
  clocks = <&cru 158>, <&cru 157>;
  clock-names = "tsadc", "apb_pclk";
  assigned-clocks = <&cru 158>;
  assigned-clock-rates = <2000000>;
  resets = <&cru 86>, <&cru 87>;
  reset-names = "tsadc-apb", "tsadc";
  rockchip,hw-tshut-temp = <120000>;
  rockchip,hw-tshut-mode = <0>;
  rockchip,hw-tshut-polarity = <0>;
  pinctrl-0 = <&tsadc_gpio_func>;
  pinctrl-1 = <&tsadc_shut>;
  pinctrl-names = "gpio", "otpout";
  #thermal-sensor-cells = <1>;
 };

 saradc: adc@fec10000 {
  compatible = "rockchip,rk3588-saradc";
  reg = <0x0 0xfec10000 0x0 0x10000>;
  interrupts = <0 398 4 0>;
  #io-channel-cells = <1>;
  clocks = <&cru 145>, <&cru 144>;
  clock-names = "saradc", "apb_pclk";
  resets = <&cru 85>;
  reset-names = "saradc-apb";
  status = "disabled";
 };

 i2c6: i2c@fec80000 {
  compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
  reg = <0x0 0xfec80000 0x0 0x1000>;
  clocks = <&cru 136>, <&cru 128>;
  clock-names = "i2c", "pclk";
  interrupts = <0 323 4 0>;
  pinctrl-0 = <&i2c6m0_xfer>;
  pinctrl-names = "default";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c7: i2c@fec90000 {
  compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
  reg = <0x0 0xfec90000 0x0 0x1000>;
  clocks = <&cru 137>, <&cru 129>;
  clock-names = "i2c", "pclk";
  interrupts = <0 324 4 0>;
  pinctrl-0 = <&i2c7m0_xfer>;
  pinctrl-names = "default";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c8: i2c@feca0000 {
  compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
  reg = <0x0 0xfeca0000 0x0 0x1000>;
  clocks = <&cru 138>, <&cru 130>;
  clock-names = "i2c", "pclk";
  interrupts = <0 325 4 0>;
  pinctrl-0 = <&i2c8m0_xfer>;
  pinctrl-names = "default";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 spi4: spi@fecb0000 {
  compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
  reg = <0x0 0xfecb0000 0x0 0x1000>;
  interrupts = <0 330 4 0>;
  clocks = <&cru 155>, <&cru 150>;
  clock-names = "spiclk", "apb_pclk";
  dmas = <&dmac2 13>, <&dmac2 14>;
  dma-names = "tx", "rx";
  num-cs = <2>;
  pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
  pinctrl-names = "default";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 otp: efuse@fecc0000 {
  compatible = "rockchip,rk3588-otp";
  reg = <0x0 0xfecc0000 0x0 0x400>;
  clocks = <&cru 140>, <&cru 139>,
    <&cru 143>, <&cru 141>;
  clock-names = "otp", "apb_pclk", "phy", "arb";
  resets = <&cru 167>, <&cru 166>,
    <&cru 168>;
  reset-names = "otp", "apb", "arb";
  #address-cells = <1>;
  #size-cells = <1>;

  cpu_code: cpu-code@2 {
   reg = <0x02 0x2>;
  };

  otp_id: id@7 {
   reg = <0x07 0x10>;
  };

  cpub0_leakage: cpu-leakage@17 {
   reg = <0x17 0x1>;
  };

  cpub1_leakage: cpu-leakage@18 {
   reg = <0x18 0x1>;
  };

  cpul_leakage: cpu-leakage@19 {
   reg = <0x19 0x1>;
  };

  log_leakage: log-leakage@1a {
   reg = <0x1a 0x1>;
  };

  gpu_leakage: gpu-leakage@1b {
   reg = <0x1b 0x1>;
  };

  otp_cpu_version: cpu-version@1c {
   reg = <0x1c 0x1>;
   bits = <3 3>;
  };

  npu_leakage: npu-leakage@28 {
   reg = <0x28 0x1>;
  };

  codec_leakage: codec-leakage@29 {
   reg = <0x29 0x1>;
  };
 };

 dmac2: dma-controller@fed10000 {
  compatible = "arm,pl330", "arm,primecell";
  reg = <0x0 0xfed10000 0x0 0x4000>;
  interrupts = <0 90 4 0>,
        <0 91 4 0>;
  arm,pl330-periph-burst;
  clocks = <&cru 112>;
  clock-names = "apb_pclk";
  #dma-cells = <1>;
 };

 usbdp_phy0: phy@fed80000 {
  compatible = "rockchip,rk3588-usbdp-phy";
  reg = <0x0 0xfed80000 0x0 0x10000>;
  rockchip,u2phy-grf = <&usb2phy0_grf>;
  rockchip,usb-grf = <&usb_grf>;
  rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
  rockchip,vo-grf = <&vo0_grf>;
  clocks = <&cru 673>,
    <&cru 620>,
    <&cru 598>,
    <&u2phy0>;
  clock-names = "refclk", "immortal", "pclk", "utmi";
  resets = <&cru 11>,
    <&cru 12>,
    <&cru 13>,
    <&cru 14>,
    <&cru 535>;
  reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
  status = "disabled";

  usbdp_phy0_dp: dp-port {
   #phy-cells = <0>;
   status = "disabled";
  };

  usbdp_phy0_u3: usb3-port {
   #phy-cells = <0>;
   status = "disabled";
  };
 };

 combphy0_ps: phy@fee00000 {
  compatible = "rockchip,rk3588-naneng-combphy";
  reg = <0x0 0xfee00000 0x0 0x100>;
  clocks = <&cru 680>, <&cru 374>,
    <&cru 343>;
  clock-names = "ref", "apb", "pipe";
  assigned-clocks = <&cru 680>;
  assigned-clock-rates = <100000000>;
  #phy-cells = <1>;
  resets = <&cru 572>, <&cru 579>;
  reset-names = "phy", "apb";
  rockchip,pipe-grf = <&php_grf>;
  rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
  status = "disabled";
 };

 combphy2_psu: phy@fee20000 {
  compatible = "rockchip,rk3588-naneng-combphy";
  reg = <0x0 0xfee20000 0x0 0x100>;
  clocks = <&cru 682>, <&cru 376>,
    <&cru 343>;
  clock-names = "ref", "apb", "pipe";
  assigned-clocks = <&cru 682>;
  assigned-clock-rates = <100000000>;
  #phy-cells = <1>;
  resets = <&cru 574>, <&cru 581>;
  reset-names = "phy", "apb";
  rockchip,pipe-grf = <&php_grf>;
  rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
  status = "disabled";
 };

 system_sram2: sram@ff001000 {
  compatible = "mmio-sram";
  reg = <0x0 0xff001000 0x0 0xef000>;
  ranges = <0x0 0x0 0xff001000 0xef000>;
  #address-cells = <1>;
  #size-cells = <1>;
 };

 pinctrl: pinctrl {
  compatible = "rockchip,rk3588-pinctrl";
  ranges;
  rockchip,grf = <&ioc>;
  #address-cells = <2>;
  #size-cells = <2>;

  gpio0: gpio@fd8a0000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xfd8a0000 0x0 0x100>;
   interrupts = <0 277 4 0>;
   clocks = <&cru 625>, <&cru 626>;
   gpio-controller;
   gpio-ranges = <&pinctrl 0 0 32>;
   interrupt-controller;
   #gpio-cells = <2>;
   #interrupt-cells = <2>;
  };

  gpio1: gpio@fec20000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xfec20000 0x0 0x100>;
   interrupts = <0 278 4 0>;
   clocks = <&cru 115>, <&cru 116>;
   gpio-controller;
   gpio-ranges = <&pinctrl 0 32 32>;
   interrupt-controller;
   #gpio-cells = <2>;
   #interrupt-cells = <2>;
  };

  gpio2: gpio@fec30000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xfec30000 0x0 0x100>;
   interrupts = <0 279 4 0>;
   clocks = <&cru 117>, <&cru 118>;
   gpio-controller;
   gpio-ranges = <&pinctrl 0 64 32>;
   interrupt-controller;
   #gpio-cells = <2>;
   #interrupt-cells = <2>;
  };

  gpio3: gpio@fec40000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xfec40000 0x0 0x100>;
   interrupts = <0 280 4 0>;
   clocks = <&cru 119>, <&cru 120>;
   gpio-controller;
   gpio-ranges = <&pinctrl 0 96 32>;
   interrupt-controller;
   #gpio-cells = <2>;
   #interrupt-cells = <2>;
  };

  gpio4: gpio@fec50000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xfec50000 0x0 0x100>;
   interrupts = <0 281 4 0>;
   clocks = <&cru 121>, <&cru 122>;
   gpio-controller;
   gpio-ranges = <&pinctrl 0 128 32>;
   interrupt-controller;
   #gpio-cells = <2>;
   #interrupt-cells = <2>;
  };
 };
};

# 1 "arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi" 1





# 1 "./scripts/dtc/include-prefixes/dt-bindings/pinctrl/rockchip.h" 1
# 7 "arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi" 2
# 1 "arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi" 1





&pinctrl {
 /omit-if-no-ref/
 pcfg_pull_up: pcfg-pull-up {
  bias-pull-up;
 };

 /omit-if-no-ref/
 pcfg_pull_down: pcfg-pull-down {
  bias-pull-down;
 };

 /omit-if-no-ref/
 pcfg_pull_none: pcfg-pull-none {
  bias-disable;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
  bias-disable;
  drive-strength = <0>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
  bias-disable;
  drive-strength = <1>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
  bias-disable;
  drive-strength = <2>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
  bias-disable;
  drive-strength = <3>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 {
  bias-disable;
  drive-strength = <4>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 {
  bias-disable;
  drive-strength = <5>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 {
  bias-disable;
  drive-strength = <6>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 {
  bias-disable;
  drive-strength = <7>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 {
  bias-disable;
  drive-strength = <8>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 {
  bias-disable;
  drive-strength = <9>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 {
  bias-disable;
  drive-strength = <10>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 {
  bias-disable;
  drive-strength = <11>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 {
  bias-disable;
  drive-strength = <12>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 {
  bias-disable;
  drive-strength = <13>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 {
  bias-disable;
  drive-strength = <14>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 {
  bias-disable;
  drive-strength = <15>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 {
  bias-pull-up;
  drive-strength = <0>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 {
  bias-pull-up;
  drive-strength = <1>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 {
  bias-pull-up;
  drive-strength = <2>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 {
  bias-pull-up;
  drive-strength = <3>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 {
  bias-pull-up;
  drive-strength = <4>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 {
  bias-pull-up;
  drive-strength = <5>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 {
  bias-pull-up;
  drive-strength = <6>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 {
  bias-pull-up;
  drive-strength = <7>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 {
  bias-pull-up;
  drive-strength = <8>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 {
  bias-pull-up;
  drive-strength = <9>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 {
  bias-pull-up;
  drive-strength = <10>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 {
  bias-pull-up;
  drive-strength = <11>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 {
  bias-pull-up;
  drive-strength = <12>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 {
  bias-pull-up;
  drive-strength = <13>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 {
  bias-pull-up;
  drive-strength = <14>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 {
  bias-pull-up;
  drive-strength = <15>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 {
  bias-pull-down;
  drive-strength = <0>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 {
  bias-pull-down;
  drive-strength = <1>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 {
  bias-pull-down;
  drive-strength = <2>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 {
  bias-pull-down;
  drive-strength = <3>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 {
  bias-pull-down;
  drive-strength = <4>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 {
  bias-pull-down;
  drive-strength = <5>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 {
  bias-pull-down;
  drive-strength = <6>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 {
  bias-pull-down;
  drive-strength = <7>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 {
  bias-pull-down;
  drive-strength = <8>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 {
  bias-pull-down;
  drive-strength = <9>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 {
  bias-pull-down;
  drive-strength = <10>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 {
  bias-pull-down;
  drive-strength = <11>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 {
  bias-pull-down;
  drive-strength = <12>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 {
  bias-pull-down;
  drive-strength = <13>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 {
  bias-pull-down;
  drive-strength = <14>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 {
  bias-pull-down;
  drive-strength = <15>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_smt: pcfg-pull-up-smt {
  bias-pull-up;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_pull_down_smt: pcfg-pull-down-smt {
  bias-pull-down;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_pull_none_smt: pcfg-pull-none-smt {
  bias-disable;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt {
  bias-disable;
  drive-strength = <0>;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_output_high: pcfg-output-high {
  output-high;
 };

 /omit-if-no-ref/
 pcfg_output_low: pcfg-output-low {
  output-low;
 };
};
# 8 "arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi" 2





&pinctrl {
 auddsm {
  /omit-if-no-ref/
  auddsm_pins: auddsm-pins {
   rockchip,pins =

    <3 1 4 &pcfg_pull_none>,

    <3 2 4 &pcfg_pull_none>,

    <3 3 4 &pcfg_pull_none>,

    <3 4 4 &pcfg_pull_none>;
  };
 };

 bt1120 {
  /omit-if-no-ref/
  bt1120_pins: bt1120-pins {
   rockchip,pins =

    <4 8 2 &pcfg_pull_none>,

    <4 0 2 &pcfg_pull_none>,

    <4 1 2 &pcfg_pull_none>,

    <4 2 2 &pcfg_pull_none>,

    <4 3 2 &pcfg_pull_none>,

    <4 4 2 &pcfg_pull_none>,

    <4 5 2 &pcfg_pull_none>,

    <4 6 2 &pcfg_pull_none>,

    <4 7 2 &pcfg_pull_none>,

    <4 10 2 &pcfg_pull_none>,

    <4 11 2 &pcfg_pull_none>,

    <4 12 2 &pcfg_pull_none>,

    <4 13 2 &pcfg_pull_none>,

    <4 14 2 &pcfg_pull_none>,

    <4 15 2 &pcfg_pull_none>,

    <4 16 2 &pcfg_pull_none>,

    <4 17 2 &pcfg_pull_none>;
  };
 };

 can0 {
  /omit-if-no-ref/
  can0m0_pins: can0m0-pins {
   rockchip,pins =

    <0 16 11 &pcfg_pull_none>,

    <0 15 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  can0m1_pins: can0m1-pins {
   rockchip,pins =

    <4 29 9 &pcfg_pull_none>,

    <4 28 9 &pcfg_pull_none>;
  };
 };

 can1 {
  /omit-if-no-ref/
  can1m0_pins: can1m0-pins {
   rockchip,pins =

    <3 13 9 &pcfg_pull_none>,

    <3 14 9 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  can1m1_pins: can1m1-pins {
   rockchip,pins =

    <4 10 12 &pcfg_pull_none>,

    <4 11 12 &pcfg_pull_none>;
  };
 };

 can2 {
  /omit-if-no-ref/
  can2m0_pins: can2m0-pins {
   rockchip,pins =

    <3 20 9 &pcfg_pull_none>,

    <3 21 9 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  can2m1_pins: can2m1-pins {
   rockchip,pins =

    <0 28 10 &pcfg_pull_none>,

    <0 29 10 &pcfg_pull_none>;
  };
 };

 cif {
  /omit-if-no-ref/
  cif_clk: cif-clk {
   rockchip,pins =

    <4 12 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  cif_dvp_clk: cif-dvp-clk {
   rockchip,pins =

    <4 8 1 &pcfg_pull_none>,

    <4 10 1 &pcfg_pull_none>,

    <4 11 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  cif_dvp_bus16: cif-dvp-bus16 {
   rockchip,pins =

    <3 20 1 &pcfg_pull_none>,

    <3 21 1 &pcfg_pull_none>,

    <3 22 1 &pcfg_pull_none>,

    <3 23 1 &pcfg_pull_none>,

    <3 24 1 &pcfg_pull_none>,

    <3 25 1 &pcfg_pull_none>,

    <3 26 1 &pcfg_pull_none>,

    <3 27 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  cif_dvp_bus8: cif-dvp-bus8 {
   rockchip,pins =

    <4 0 1 &pcfg_pull_none>,

    <4 1 1 &pcfg_pull_none>,

    <4 2 1 &pcfg_pull_none>,

    <4 3 1 &pcfg_pull_none>,

    <4 4 1 &pcfg_pull_none>,

    <4 5 1 &pcfg_pull_none>,

    <4 6 1 &pcfg_pull_none>,

    <4 7 1 &pcfg_pull_none>;
  };
 };

 clk32k {
  /omit-if-no-ref/
  clk32k_in: clk32k-in {
   rockchip,pins =

    <0 10 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  clk32k_out0: clk32k-out0 {
   rockchip,pins =

    <0 10 2 &pcfg_pull_none>;
  };
 };

 cpu {
  /omit-if-no-ref/
  cpu_pins: cpu-pins {
   rockchip,pins =

    <0 25 2 &pcfg_pull_none>,

    <0 29 2 &pcfg_pull_none>;
  };
 };

 ddrphych0 {
  /omit-if-no-ref/
  ddrphych0_pins: ddrphych0-pins {
   rockchip,pins =

    <4 0 7 &pcfg_pull_none>,

    <4 1 7 &pcfg_pull_none>,

    <4 2 7 &pcfg_pull_none>,

    <4 3 7 &pcfg_pull_none>;
  };
 };

 ddrphych1 {
  /omit-if-no-ref/
  ddrphych1_pins: ddrphych1-pins {
   rockchip,pins =

    <4 4 7 &pcfg_pull_none>,

    <4 5 7 &pcfg_pull_none>,

    <4 6 7 &pcfg_pull_none>,

    <4 7 7 &pcfg_pull_none>;
  };
 };

 ddrphych2 {
  /omit-if-no-ref/
  ddrphych2_pins: ddrphych2-pins {
   rockchip,pins =

    <4 8 7 &pcfg_pull_none>,

    <4 9 7 &pcfg_pull_none>,

    <4 10 7 &pcfg_pull_none>,

    <4 11 7 &pcfg_pull_none>;
  };
 };

 ddrphych3 {
  /omit-if-no-ref/
  ddrphych3_pins: ddrphych3-pins {
   rockchip,pins =

    <4 12 7 &pcfg_pull_none>,

    <4 13 7 &pcfg_pull_none>,

    <4 14 7 &pcfg_pull_none>,

    <4 15 7 &pcfg_pull_none>;
  };
 };

 dp0 {
  /omit-if-no-ref/
  dp0m0_pins: dp0m0-pins {
   rockchip,pins =

    <4 12 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  dp0m1_pins: dp0m1-pins {
   rockchip,pins =

    <0 20 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  dp0m2_pins: dp0m2-pins {
   rockchip,pins =

    <1 0 5 &pcfg_pull_none>;
  };
 };

 dp1 {
  /omit-if-no-ref/
  dp1m0_pins: dp1m0-pins {
   rockchip,pins =

    <3 29 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  dp1m1_pins: dp1m1-pins {
   rockchip,pins =

    <0 21 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  dp1m2_pins: dp1m2-pins {
   rockchip,pins =

    <1 1 5 &pcfg_pull_none>;
  };
 };

 emmc {
  /omit-if-no-ref/
  emmc_rstnout: emmc-rstnout {
   rockchip,pins =

    <2 3 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  emmc_bus8: emmc-bus8 {
   rockchip,pins =

    <2 24 1 &pcfg_pull_up_drv_level_2>,

    <2 25 1 &pcfg_pull_up_drv_level_2>,

    <2 26 1 &pcfg_pull_up_drv_level_2>,

    <2 27 1 &pcfg_pull_up_drv_level_2>,

    <2 28 1 &pcfg_pull_up_drv_level_2>,

    <2 29 1 &pcfg_pull_up_drv_level_2>,

    <2 30 1 &pcfg_pull_up_drv_level_2>,

    <2 31 1 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  emmc_clk: emmc-clk {
   rockchip,pins =

    <2 1 1 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  emmc_cmd: emmc-cmd {
   rockchip,pins =

    <2 0 1 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  emmc_data_strobe: emmc-data-strobe {
   rockchip,pins =

    <2 2 1 &pcfg_pull_none>;
  };
 };

 eth1 {
  /omit-if-no-ref/
  eth1_pins: eth1-pins {
   rockchip,pins =

    <3 6 1 &pcfg_pull_none>;
  };
 };

 fspi {
  /omit-if-no-ref/
  fspim0_pins: fspim0-pins {
   rockchip,pins =

    <2 0 2 &pcfg_pull_up_drv_level_2>,

    <2 30 2 &pcfg_pull_up_drv_level_2>,

    <2 24 2 &pcfg_pull_up_drv_level_2>,

    <2 25 2 &pcfg_pull_up_drv_level_2>,

    <2 26 2 &pcfg_pull_up_drv_level_2>,

    <2 27 2 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  fspim0_cs1: fspim0-cs1 {
   rockchip,pins =

    <2 31 2 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  fspim2_pins: fspim2-pins {
   rockchip,pins =

    <3 5 5 &pcfg_pull_up_drv_level_2>,

    <3 20 2 &pcfg_pull_up_drv_level_2>,

    <3 0 5 &pcfg_pull_up_drv_level_2>,

    <3 1 5 &pcfg_pull_up_drv_level_2>,

    <3 2 5 &pcfg_pull_up_drv_level_2>,

    <3 3 5 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  fspim2_cs1: fspim2-cs1 {
   rockchip,pins =

    <3 21 2 &pcfg_pull_up_drv_level_2>;
  };
 };

 gmac1 {
  /omit-if-no-ref/
  gmac1_miim: gmac1-miim {
   rockchip,pins =

    <3 18 1 &pcfg_pull_none>,

    <3 19 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1_clkinout: gmac1-clkinout {
   rockchip,pins =

    <3 14 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1_rx_bus2: gmac1-rx-bus2 {
   rockchip,pins =

    <3 7 1 &pcfg_pull_none>,

    <3 8 1 &pcfg_pull_none>,

    <3 9 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1_tx_bus2: gmac1-tx-bus2 {
   rockchip,pins =

    <3 11 1 &pcfg_pull_none>,

    <3 12 1 &pcfg_pull_none>,

    <3 13 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1_rgmii_clk: gmac1-rgmii-clk {
   rockchip,pins =

    <3 5 1 &pcfg_pull_none>,

    <3 4 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1_rgmii_bus: gmac1-rgmii-bus {
   rockchip,pins =

    <3 2 1 &pcfg_pull_none>,

    <3 3 1 &pcfg_pull_none>,

    <3 0 1 &pcfg_pull_none>,

    <3 1 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1_ppsclk: gmac1-ppsclk {
   rockchip,pins =

    <3 17 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1_ppstrig: gmac1-ppstrig {
   rockchip,pins =

    <3 16 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1_ptp_ref_clk: gmac1-ptp-ref-clk {
   rockchip,pins =

    <3 15 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1_txer: gmac1-txer {
   rockchip,pins =

    <3 10 1 &pcfg_pull_none>;
  };
 };

 gpu {
  /omit-if-no-ref/
  gpu_pins: gpu-pins {
   rockchip,pins =

    <0 21 2 &pcfg_pull_none>;
  };
 };

 hdmi {
  /omit-if-no-ref/
  hdmim0_rx_cec: hdmim0-rx-cec {
   rockchip,pins =

    <4 13 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim0_rx_hpdin: hdmim0-rx-hpdin {
   rockchip,pins =

    <4 14 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim0_rx_scl: hdmim0-rx-scl {
   rockchip,pins =

    <0 26 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim0_rx_sda: hdmim0-rx-sda {
   rockchip,pins =

    <0 25 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim0_tx0_cec: hdmim0-tx0-cec {
   rockchip,pins =

    <4 17 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim0_tx0_hpd: hdmim0-tx0-hpd {
   rockchip,pins =

    <1 5 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim0_tx0_scl: hdmim0-tx0-scl {
   rockchip,pins =

    <4 15 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim0_tx0_sda: hdmim0-tx0-sda {
   rockchip,pins =

    <4 16 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim0_tx1_hpd: hdmim0-tx1-hpd {
   rockchip,pins =

    <1 6 5 &pcfg_pull_none>;
  };
  /omit-if-no-ref/
  hdmim1_rx_cec: hdmim1-rx-cec {
   rockchip,pins =

    <3 25 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim1_rx_hpdin: hdmim1-rx-hpdin {
   rockchip,pins =

    <3 28 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim1_rx_scl: hdmim1-rx-scl {
   rockchip,pins =

    <3 26 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim1_rx_sda: hdmim1-rx-sda {
   rockchip,pins =

    <3 27 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim1_tx0_cec: hdmim1-tx0-cec {
   rockchip,pins =

    <0 25 13 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim1_tx0_hpd: hdmim1-tx0-hpd {
   rockchip,pins =

    <3 28 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim1_tx0_scl: hdmim1-tx0-scl {
   rockchip,pins =

    <0 29 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim1_tx0_sda: hdmim1-tx0-sda {
   rockchip,pins =

    <0 28 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim1_tx1_cec: hdmim1-tx1-cec {
   rockchip,pins =

    <0 26 13 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim1_tx1_hpd: hdmim1-tx1-hpd {
   rockchip,pins =

    <3 15 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim1_tx1_scl: hdmim1-tx1-scl {
   rockchip,pins =

    <3 22 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim1_tx1_sda: hdmim1-tx1-sda {
   rockchip,pins =

    <3 21 5 &pcfg_pull_none>;
  };
  /omit-if-no-ref/
  hdmim2_rx_cec: hdmim2-rx-cec {
   rockchip,pins =

    <1 15 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim2_rx_hpdin: hdmim2-rx-hpdin {
   rockchip,pins =

    <1 14 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim2_rx_scl: hdmim2-rx-scl {
   rockchip,pins =

    <1 30 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim2_rx_sda: hdmim2-rx-sda {
   rockchip,pins =

    <1 31 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim2_tx0_scl: hdmim2-tx0-scl {
   rockchip,pins =

    <3 23 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim2_tx0_sda: hdmim2-tx0-sda {
   rockchip,pins =

    <3 24 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim2_tx1_cec: hdmim2-tx1-cec {
   rockchip,pins =

    <3 20 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim2_tx1_scl: hdmim2-tx1-scl {
   rockchip,pins =

    <1 4 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim2_tx1_sda: hdmim2-tx1-sda {
   rockchip,pins =

    <1 3 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmi_debug0: hdmi-debug0 {
   rockchip,pins =

    <1 7 7 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmi_debug1: hdmi-debug1 {
   rockchip,pins =

    <1 8 7 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmi_debug2: hdmi-debug2 {
   rockchip,pins =

    <1 9 7 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmi_debug3: hdmi-debug3 {
   rockchip,pins =

    <1 10 7 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmi_debug4: hdmi-debug4 {
   rockchip,pins =

    <1 11 7 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmi_debug5: hdmi-debug5 {
   rockchip,pins =

    <1 12 7 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmi_debug6: hdmi-debug6 {
   rockchip,pins =

    <1 0 7 &pcfg_pull_none>;
  };
 };

 i2c0 {
  /omit-if-no-ref/
  i2c0m0_xfer: i2c0m0-xfer {
   rockchip,pins =

    <0 11 2 &pcfg_pull_none_smt>,

    <0 6 2 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c0m2_xfer: i2c0m2-xfer {
   rockchip,pins =

    <0 25 3 &pcfg_pull_none_smt>,

    <0 26 3 &pcfg_pull_none_smt>;
  };
 };

 i2c1 {
  /omit-if-no-ref/
  i2c1m0_xfer: i2c1m0-xfer {
   rockchip,pins =

    <0 13 9 &pcfg_pull_none_smt>,

    <0 14 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c1m1_xfer: i2c1m1-xfer {
   rockchip,pins =

    <0 8 2 &pcfg_pull_none_smt>,

    <0 9 2 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c1m2_xfer: i2c1m2-xfer {
   rockchip,pins =

    <0 28 9 &pcfg_pull_none_smt>,

    <0 29 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c1m3_xfer: i2c1m3-xfer {
   rockchip,pins =

    <2 28 9 &pcfg_pull_none_smt>,

    <2 29 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c1m4_xfer: i2c1m4-xfer {
   rockchip,pins =

    <1 26 9 &pcfg_pull_none_smt>,

    <1 27 9 &pcfg_pull_none_smt>;
  };
 };

 i2c2 {
  /omit-if-no-ref/
  i2c2m0_xfer: i2c2m0-xfer {
   rockchip,pins =

    <0 15 9 &pcfg_pull_none_smt>,

    <0 16 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c2m2_xfer: i2c2m2-xfer {
   rockchip,pins =

    <2 3 9 &pcfg_pull_none_smt>,

    <2 2 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c2m3_xfer: i2c2m3-xfer {
   rockchip,pins =

    <1 21 9 &pcfg_pull_none_smt>,

    <1 20 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c2m4_xfer: i2c2m4-xfer {
   rockchip,pins =

    <1 1 9 &pcfg_pull_none_smt>,

    <1 0 9 &pcfg_pull_none_smt>;
  };
 };

 i2c3 {
  /omit-if-no-ref/
  i2c3m0_xfer: i2c3m0-xfer {
   rockchip,pins =

    <1 17 9 &pcfg_pull_none_smt>,

    <1 16 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c3m1_xfer: i2c3m1-xfer {
   rockchip,pins =

    <3 15 9 &pcfg_pull_none_smt>,

    <3 16 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c3m2_xfer: i2c3m2-xfer {
   rockchip,pins =

    <4 4 9 &pcfg_pull_none_smt>,

    <4 5 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c3m4_xfer: i2c3m4-xfer {
   rockchip,pins =

    <4 24 9 &pcfg_pull_none_smt>,

    <4 25 9 &pcfg_pull_none_smt>;
  };
 };

 i2c4 {
  /omit-if-no-ref/
  i2c4m0_xfer: i2c4m0-xfer {
   rockchip,pins =

    <3 6 9 &pcfg_pull_none_smt>,

    <3 5 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c4m2_xfer: i2c4m2-xfer {
   rockchip,pins =

    <0 21 9 &pcfg_pull_none_smt>,

    <0 20 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c4m3_xfer: i2c4m3-xfer {
   rockchip,pins =

    <1 3 9 &pcfg_pull_none_smt>,

    <1 2 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c4m4_xfer: i2c4m4-xfer {
   rockchip,pins =

    <1 23 9 &pcfg_pull_none_smt>,

    <1 22 9 &pcfg_pull_none_smt>;
  };
 };

 i2c5 {
  /omit-if-no-ref/
  i2c5m0_xfer: i2c5m0-xfer {
   rockchip,pins =

    <3 23 9 &pcfg_pull_none_smt>,

    <3 24 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c5m1_xfer: i2c5m1-xfer {
   rockchip,pins =

    <4 14 9 &pcfg_pull_none_smt>,

    <4 15 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c5m2_xfer: i2c5m2-xfer {
   rockchip,pins =

    <4 6 9 &pcfg_pull_none_smt>,

    <4 7 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c5m3_xfer: i2c5m3-xfer {
   rockchip,pins =

    <1 14 9 &pcfg_pull_none_smt>,

    <1 15 9 &pcfg_pull_none_smt>;
  };
 };

 i2c6 {
  /omit-if-no-ref/
  i2c6m0_xfer: i2c6m0-xfer {
   rockchip,pins =

    <0 24 9 &pcfg_pull_none_smt>,

    <0 23 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c6m1_xfer: i2c6m1-xfer {
   rockchip,pins =

    <1 19 9 &pcfg_pull_none_smt>,

    <1 18 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c6m3_xfer: i2c6m3-xfer {
   rockchip,pins =

    <4 9 9 &pcfg_pull_none_smt>,

    <4 8 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c6m4_xfer: i2c6m4-xfer {
   rockchip,pins =

    <3 1 9 &pcfg_pull_none_smt>,

    <3 0 9 &pcfg_pull_none_smt>;
  };
 };

 i2c7 {
  /omit-if-no-ref/
  i2c7m0_xfer: i2c7m0-xfer {
   rockchip,pins =

    <1 24 9 &pcfg_pull_none_smt>,

    <1 25 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c7m2_xfer: i2c7m2-xfer {
   rockchip,pins =

    <3 26 9 &pcfg_pull_none_smt>,

    <3 27 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c7m3_xfer: i2c7m3-xfer {
   rockchip,pins =

    <4 10 9 &pcfg_pull_none_smt>,

    <4 11 9 &pcfg_pull_none_smt>;
  };
 };

 i2c8 {
  /omit-if-no-ref/
  i2c8m0_xfer: i2c8m0-xfer {
   rockchip,pins =

    <4 26 9 &pcfg_pull_none_smt>,

    <4 27 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c8m2_xfer: i2c8m2-xfer {
   rockchip,pins =

    <1 30 9 &pcfg_pull_none_smt>,

    <1 31 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c8m3_xfer: i2c8m3-xfer {
   rockchip,pins =

    <4 16 9 &pcfg_pull_none_smt>,

    <4 17 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c8m4_xfer: i2c8m4-xfer {
   rockchip,pins =

    <3 18 9 &pcfg_pull_none_smt>,

    <3 19 9 &pcfg_pull_none_smt>;
  };
 };

 i2s0 {
  /omit-if-no-ref/
  i2s0_lrck: i2s0-lrck {
   rockchip,pins =

    <1 21 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s0_mclk: i2s0-mclk {
   rockchip,pins =

    <1 18 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s0_sclk: i2s0-sclk {
   rockchip,pins =

    <1 19 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s0_sdi0: i2s0-sdi0 {
   rockchip,pins =

    <1 28 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s0_sdi1: i2s0-sdi1 {
   rockchip,pins =

    <1 27 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s0_sdi2: i2s0-sdi2 {
   rockchip,pins =

    <1 26 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s0_sdi3: i2s0-sdi3 {
   rockchip,pins =

    <1 25 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s0_sdo0: i2s0-sdo0 {
   rockchip,pins =

    <1 23 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s0_sdo1: i2s0-sdo1 {
   rockchip,pins =

    <1 24 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s0_sdo2: i2s0-sdo2 {
   rockchip,pins =

    <1 25 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s0_sdo3: i2s0-sdo3 {
   rockchip,pins =

    <1 26 1 &pcfg_pull_none>;
  };
 };

 i2s1 {
  /omit-if-no-ref/
  i2s1m0_lrck: i2s1m0-lrck {
   rockchip,pins =

    <4 2 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_mclk: i2s1m0-mclk {
   rockchip,pins =

    <4 0 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_sclk: i2s1m0-sclk {
   rockchip,pins =

    <4 1 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_sdi0: i2s1m0-sdi0 {
   rockchip,pins =

    <4 5 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_sdi1: i2s1m0-sdi1 {
   rockchip,pins =

    <4 6 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_sdi2: i2s1m0-sdi2 {
   rockchip,pins =

    <4 7 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_sdi3: i2s1m0-sdi3 {
   rockchip,pins =

    <4 8 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_sdo0: i2s1m0-sdo0 {
   rockchip,pins =

    <4 9 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_sdo1: i2s1m0-sdo1 {
   rockchip,pins =

    <4 10 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_sdo2: i2s1m0-sdo2 {
   rockchip,pins =

    <4 11 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_sdo3: i2s1m0-sdo3 {
   rockchip,pins =

    <4 12 3 &pcfg_pull_none>;
  };
  /omit-if-no-ref/
  i2s1m1_lrck: i2s1m1-lrck {
   rockchip,pins =

    <0 15 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_mclk: i2s1m1-mclk {
   rockchip,pins =

    <0 13 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_sclk: i2s1m1-sclk {
   rockchip,pins =

    <0 14 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_sdi0: i2s1m1-sdi0 {
   rockchip,pins =

    <0 21 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_sdi1: i2s1m1-sdi1 {
   rockchip,pins =

    <0 22 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_sdi2: i2s1m1-sdi2 {
   rockchip,pins =

    <0 23 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_sdi3: i2s1m1-sdi3 {
   rockchip,pins =

    <0 24 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_sdo0: i2s1m1-sdo0 {
   rockchip,pins =

    <0 25 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_sdo1: i2s1m1-sdo1 {
   rockchip,pins =

    <0 26 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_sdo2: i2s1m1-sdo2 {
   rockchip,pins =

    <0 28 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_sdo3: i2s1m1-sdo3 {
   rockchip,pins =

    <0 29 1 &pcfg_pull_none>;
  };
 };

 i2s2 {
  /omit-if-no-ref/
  i2s2m0_lrck: i2s2m0-lrck {
   rockchip,pins =

    <2 16 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m0_mclk: i2s2m0-mclk {
   rockchip,pins =

    <2 14 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m0_sclk: i2s2m0-sclk {
   rockchip,pins =

    <2 15 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m0_sdi: i2s2m0-sdi {
   rockchip,pins =

    <2 19 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m0_sdo: i2s2m0-sdo {
   rockchip,pins =

    <4 19 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m1_lrck: i2s2m1-lrck {
   rockchip,pins =

    <3 14 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m1_mclk: i2s2m1-mclk {
   rockchip,pins =

    <3 12 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m1_sclk: i2s2m1-sclk {
   rockchip,pins =

    <3 13 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m1_sdi: i2s2m1-sdi {
   rockchip,pins =

    <3 10 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m1_sdo: i2s2m1-sdo {
   rockchip,pins =

    <3 11 3 &pcfg_pull_none>;
  };
 };

 i2s3 {
  /omit-if-no-ref/
  i2s3_lrck: i2s3-lrck {
   rockchip,pins =

    <3 2 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s3_mclk: i2s3-mclk {
   rockchip,pins =

    <3 0 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s3_sclk: i2s3-sclk {
   rockchip,pins =

    <3 1 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s3_sdi: i2s3-sdi {
   rockchip,pins =

    <3 4 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s3_sdo: i2s3-sdo {
   rockchip,pins =

    <3 3 3 &pcfg_pull_none>;
  };
 };

 jtag {
  /omit-if-no-ref/
  jtagm0_pins: jtagm0-pins {
   rockchip,pins =

    <4 26 5 &pcfg_pull_none>,

    <4 27 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  jtagm1_pins: jtagm1-pins {
   rockchip,pins =

    <4 24 5 &pcfg_pull_none>,

    <4 25 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  jtagm2_pins: jtagm2-pins {
   rockchip,pins =

    <0 13 2 &pcfg_pull_none>,

    <0 14 2 &pcfg_pull_none>;
  };
 };

 litcpu {
  /omit-if-no-ref/
  litcpu_pins: litcpu-pins {
   rockchip,pins =

    <0 27 1 &pcfg_pull_none>;
  };
 };

 mcu {
  /omit-if-no-ref/
  mcum0_pins: mcum0-pins {
   rockchip,pins =

    <4 28 5 &pcfg_pull_none>,

    <4 29 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  mcum1_pins: mcum1-pins {
   rockchip,pins =

    <3 28 6 &pcfg_pull_none>,

    <3 29 6 &pcfg_pull_none>;
  };
 };

 mipi {
  /omit-if-no-ref/
  mipim0_camera0_clk: mipim0-camera0-clk {
   rockchip,pins =

    <4 9 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  mipim0_camera1_clk: mipim0-camera1-clk {
   rockchip,pins =

    <1 14 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  mipim0_camera2_clk: mipim0-camera2-clk {
   rockchip,pins =

    <1 15 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  mipim0_camera3_clk: mipim0-camera3-clk {
   rockchip,pins =

    <1 30 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  mipim0_camera4_clk: mipim0-camera4-clk {
   rockchip,pins =

    <1 31 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  mipim1_camera0_clk: mipim1-camera0-clk {
   rockchip,pins =

    <3 5 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  mipim1_camera1_clk: mipim1-camera1-clk {
   rockchip,pins =

    <3 6 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  mipim1_camera2_clk: mipim1-camera2-clk {
   rockchip,pins =

    <3 7 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  mipim1_camera3_clk: mipim1-camera3-clk {
   rockchip,pins =

    <3 8 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  mipim1_camera4_clk: mipim1-camera4-clk {
   rockchip,pins =

    <3 9 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  mipi_te0: mipi-te0 {
   rockchip,pins =

    <3 18 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  mipi_te1: mipi-te1 {
   rockchip,pins =

    <3 19 2 &pcfg_pull_none>;
  };
 };

 npu {
  /omit-if-no-ref/
  npu_pins: npu-pins {
   rockchip,pins =

    <0 22 2 &pcfg_pull_none>;
  };
 };

 pcie20x1 {
  /omit-if-no-ref/
  pcie20x1m0_pins: pcie20x1m0-pins {
   rockchip,pins =

    <3 23 4 &pcfg_pull_none>,

    <3 25 4 &pcfg_pull_none>,

    <3 24 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie20x1m1_pins: pcie20x1m1-pins {
   rockchip,pins =

    <4 15 4 &pcfg_pull_none>,

    <4 17 4 &pcfg_pull_none>,

    <4 16 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie20x1_2_button_rstn: pcie20x1-2-button-rstn {
   rockchip,pins =

    <4 11 4 &pcfg_pull_none>;
  };
 };

 pcie30phy {
  /omit-if-no-ref/
  pcie30phy_pins: pcie30phy-pins {
   rockchip,pins =

    <1 20 4 &pcfg_pull_none>,

    <1 25 4 &pcfg_pull_none>;
  };
 };

 pcie30x1 {
  /omit-if-no-ref/
  pcie30x1m0_pins: pcie30x1m0-pins {
   rockchip,pins =

    <0 16 12 &pcfg_pull_none>,

    <0 21 12 &pcfg_pull_none>,

    <0 20 12 &pcfg_pull_none>,

    <0 13 12 &pcfg_pull_none>,

    <0 15 12 &pcfg_pull_none>,

    <0 14 12 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x1m1_pins: pcie30x1m1-pins {
   rockchip,pins =

    <4 3 4 &pcfg_pull_none>,

    <4 5 4 &pcfg_pull_none>,

    <4 4 4 &pcfg_pull_none>,

    <4 0 4 &pcfg_pull_none>,

    <4 2 4 &pcfg_pull_none>,

    <4 1 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x1m2_pins: pcie30x1m2-pins {
   rockchip,pins =

    <1 13 4 &pcfg_pull_none>,

    <1 12 4 &pcfg_pull_none>,

    <1 11 4 &pcfg_pull_none>,

    <1 0 4 &pcfg_pull_none>,

    <1 7 4 &pcfg_pull_none>,

    <1 1 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x1_0_button_rstn: pcie30x1-0-button-rstn {
   rockchip,pins =

    <4 9 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x1_1_button_rstn: pcie30x1-1-button-rstn {
   rockchip,pins =

    <4 10 4 &pcfg_pull_none>;
  };
 };

 pcie30x2 {
  /omit-if-no-ref/
  pcie30x2m0_pins: pcie30x2m0-pins {
   rockchip,pins =

    <0 25 12 &pcfg_pull_none>,

    <0 28 12 &pcfg_pull_none>,

    <0 26 12 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x2m1_pins: pcie30x2m1-pins {
   rockchip,pins =

    <4 6 4 &pcfg_pull_none>,

    <4 8 4 &pcfg_pull_none>,

    <4 7 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x2m2_pins: pcie30x2m2-pins {
   rockchip,pins =

    <3 26 4 &pcfg_pull_none>,

    <3 28 4 &pcfg_pull_none>,

    <3 27 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x2m3_pins: pcie30x2m3-pins {
   rockchip,pins =

    <1 31 4 &pcfg_pull_none>,

    <1 15 4 &pcfg_pull_none>,

    <1 14 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x2_button_rstn: pcie30x2-button-rstn {
   rockchip,pins =

    <3 17 4 &pcfg_pull_none>;
  };
 };

 pcie30x4 {
  /omit-if-no-ref/
  pcie30x4m0_pins: pcie30x4m0-pins {
   rockchip,pins =

    <0 22 12 &pcfg_pull_none>,

    <0 24 12 &pcfg_pull_none>,

    <0 23 12 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x4m1_pins: pcie30x4m1-pins {
   rockchip,pins =

    <4 12 4 &pcfg_pull_none>,

    <4 14 4 &pcfg_pull_none>,

    <4 13 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x4m2_pins: pcie30x4m2-pins {
   rockchip,pins =

    <3 20 4 &pcfg_pull_none>,

    <3 22 4 &pcfg_pull_none>,

    <3 21 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x4m3_pins: pcie30x4m3-pins {
   rockchip,pins =

    <1 8 4 &pcfg_pull_none>,

    <1 10 4 &pcfg_pull_none>,

    <1 9 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x4_button_rstn: pcie30x4-button-rstn {
   rockchip,pins =

    <3 29 4 &pcfg_pull_none>;
  };
 };

 pdm0 {
  /omit-if-no-ref/
  pdm0m0_clk: pdm0m0-clk {
   rockchip,pins =

    <1 22 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm0m0_clk1: pdm0m0-clk1 {
   rockchip,pins =

    <1 20 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm0m0_sdi0: pdm0m0-sdi0 {
   rockchip,pins =

    <1 29 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm0m0_sdi1: pdm0m0-sdi1 {
   rockchip,pins =

    <1 25 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm0m0_sdi2: pdm0m0-sdi2 {
   rockchip,pins =

    <1 26 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm0m0_sdi3: pdm0m0-sdi3 {
   rockchip,pins =

    <1 27 3 &pcfg_pull_none>;
  };
  /omit-if-no-ref/
  pdm0m1_clk: pdm0m1-clk {
   rockchip,pins =

    <0 16 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm0m1_clk1: pdm0m1-clk1 {
   rockchip,pins =

    <0 20 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm0m1_sdi0: pdm0m1-sdi0 {
   rockchip,pins =

    <0 23 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm0m1_sdi1: pdm0m1-sdi1 {
   rockchip,pins =

    <0 24 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm0m1_sdi2: pdm0m1-sdi2 {
   rockchip,pins =

    <0 28 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm0m1_sdi3: pdm0m1-sdi3 {
   rockchip,pins =

    <0 30 2 &pcfg_pull_none>;
  };
 };

 pdm1 {
  /omit-if-no-ref/
  pdm1m0_clk: pdm1m0-clk {
   rockchip,pins =

    <4 29 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm1m0_clk1: pdm1m0-clk1 {
   rockchip,pins =

    <4 28 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm1m0_sdi0: pdm1m0-sdi0 {
   rockchip,pins =

    <4 27 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm1m0_sdi1: pdm1m0-sdi1 {
   rockchip,pins =

    <4 26 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm1m0_sdi2: pdm1m0-sdi2 {
   rockchip,pins =

    <4 25 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm1m0_sdi3: pdm1m0-sdi3 {
   rockchip,pins =

    <4 24 2 &pcfg_pull_none>;
  };
  /omit-if-no-ref/
  pdm1m1_clk: pdm1m1-clk {
   rockchip,pins =

    <1 12 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm1m1_clk1: pdm1m1-clk1 {
   rockchip,pins =

    <1 11 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm1m1_sdi0: pdm1m1-sdi0 {
   rockchip,pins =

    <1 7 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm1m1_sdi1: pdm1m1-sdi1 {
   rockchip,pins =

    <1 8 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm1m1_sdi2: pdm1m1-sdi2 {
   rockchip,pins =

    <1 9 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm1m1_sdi3: pdm1m1-sdi3 {
   rockchip,pins =

    <1 10 2 &pcfg_pull_none>;
  };
 };

 pmic {
  /omit-if-no-ref/
  pmic_pins: pmic-pins {
   rockchip,pins =

    <0 7 0 &pcfg_pull_up>,

    <0 2 1 &pcfg_pull_none>,

    <0 3 1 &pcfg_pull_none>,

    <0 17 1 &pcfg_pull_none>,

    <0 18 1 &pcfg_pull_none>,

    <0 19 1 &pcfg_pull_none>,

    <0 30 1 &pcfg_pull_none>;
  };
 };

 pmu {
  /omit-if-no-ref/
  pmu_pins: pmu-pins {
   rockchip,pins =

    <0 5 3 &pcfg_pull_none>;
  };
 };

 pwm0 {
  /omit-if-no-ref/
  pwm0m0_pins: pwm0m0-pins {
   rockchip,pins =

    <0 15 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm0m1_pins: pwm0m1-pins {
   rockchip,pins =

    <1 26 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm0m2_pins: pwm0m2-pins {
   rockchip,pins =

    <1 2 11 &pcfg_pull_none>;
  };
 };

 pwm1 {
  /omit-if-no-ref/
  pwm1m0_pins: pwm1m0-pins {
   rockchip,pins =

    <0 16 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm1m1_pins: pwm1m1-pins {
   rockchip,pins =

    <1 27 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm1m2_pins: pwm1m2-pins {
   rockchip,pins =

    <1 3 11 &pcfg_pull_none>;
  };
 };

 pwm2 {
  /omit-if-no-ref/
  pwm2m0_pins: pwm2m0-pins {
   rockchip,pins =

    <0 20 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm2m1_pins: pwm2m1-pins {
   rockchip,pins =

    <3 9 11 &pcfg_pull_none>;
  };
 };

 pwm3 {
  /omit-if-no-ref/
  pwm3m0_pins: pwm3m0-pins {
   rockchip,pins =

    <0 28 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm3m1_pins: pwm3m1-pins {
   rockchip,pins =

    <3 10 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm3m2_pins: pwm3m2-pins {
   rockchip,pins =

    <1 18 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm3m3_pins: pwm3m3-pins {
   rockchip,pins =

    <1 7 11 &pcfg_pull_none>;
  };
 };

 pwm4 {
  /omit-if-no-ref/
  pwm4m0_pins: pwm4m0-pins {
   rockchip,pins =

    <0 21 11 &pcfg_pull_none>;
  };
 };

 pwm5 {
  /omit-if-no-ref/
  pwm5m0_pins: pwm5m0-pins {
   rockchip,pins =

    <0 9 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm5m1_pins: pwm5m1-pins {
   rockchip,pins =

    <0 22 11 &pcfg_pull_none>;
  };
 };

 pwm6 {
  /omit-if-no-ref/
  pwm6m0_pins: pwm6m0-pins {
   rockchip,pins =

    <0 23 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm6m1_pins: pwm6m1-pins {
   rockchip,pins =

    <4 17 11 &pcfg_pull_none>;
  };
 };

 pwm7 {
  /omit-if-no-ref/
  pwm7m0_pins: pwm7m0-pins {
   rockchip,pins =

    <0 24 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm7m1_pins: pwm7m1-pins {
   rockchip,pins =

    <4 28 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm7m2_pins: pwm7m2-pins {
   rockchip,pins =

    <1 19 11 &pcfg_pull_none>;
  };
 };

 pwm8 {
  /omit-if-no-ref/
  pwm8m0_pins: pwm8m0-pins {
   rockchip,pins =

    <3 7 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm8m1_pins: pwm8m1-pins {
   rockchip,pins =

    <4 24 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm8m2_pins: pwm8m2-pins {
   rockchip,pins =

    <3 24 11 &pcfg_pull_none>;
  };
 };

 pwm9 {
  /omit-if-no-ref/
  pwm9m0_pins: pwm9m0-pins {
   rockchip,pins =

    <3 8 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm9m1_pins: pwm9m1-pins {
   rockchip,pins =

    <4 25 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm9m2_pins: pwm9m2-pins {
   rockchip,pins =

    <3 25 11 &pcfg_pull_none>;
  };
 };

 pwm10 {
  /omit-if-no-ref/
  pwm10m0_pins: pwm10m0-pins {
   rockchip,pins =

    <3 0 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm10m1_pins: pwm10m1-pins {
   rockchip,pins =

    <4 27 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm10m2_pins: pwm10m2-pins {
   rockchip,pins =

    <3 27 11 &pcfg_pull_none>;
  };
 };

 pwm11 {
  /omit-if-no-ref/
  pwm11m0_pins: pwm11m0-pins {
   rockchip,pins =

    <3 1 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm11m1_pins: pwm11m1-pins {
   rockchip,pins =

    <4 12 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm11m2_pins: pwm11m2-pins {
   rockchip,pins =

    <1 20 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm11m3_pins: pwm11m3-pins {
   rockchip,pins =

    <3 29 11 &pcfg_pull_none>;
  };
 };

 pwm12 {
  /omit-if-no-ref/
  pwm12m0_pins: pwm12m0-pins {
   rockchip,pins =

    <3 13 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm12m1_pins: pwm12m1-pins {
   rockchip,pins =

    <4 13 11 &pcfg_pull_none>;
  };
 };

 pwm13 {
  /omit-if-no-ref/
  pwm13m0_pins: pwm13m0-pins {
   rockchip,pins =

    <3 14 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm13m1_pins: pwm13m1-pins {
   rockchip,pins =

    <4 14 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm13m2_pins: pwm13m2-pins {
   rockchip,pins =

    <1 15 11 &pcfg_pull_none>;
  };
 };

 pwm14 {
  /omit-if-no-ref/
  pwm14m0_pins: pwm14m0-pins {
   rockchip,pins =

    <3 18 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm14m1_pins: pwm14m1-pins {
   rockchip,pins =

    <4 10 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm14m2_pins: pwm14m2-pins {
   rockchip,pins =

    <1 30 11 &pcfg_pull_none>;
  };
 };

 pwm15 {
  /omit-if-no-ref/
  pwm15m0_pins: pwm15m0-pins {
   rockchip,pins =

    <3 19 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm15m1_pins: pwm15m1-pins {
   rockchip,pins =

    <4 11 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm15m2_pins: pwm15m2-pins {
   rockchip,pins =

    <1 22 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm15m3_pins: pwm15m3-pins {
   rockchip,pins =

    <1 31 11 &pcfg_pull_none>;
  };
 };

 refclk {
  /omit-if-no-ref/
  refclk_pins: refclk-pins {
   rockchip,pins =

    <0 0 1 &pcfg_pull_none>;
  };
 };

 sata {
  /omit-if-no-ref/
  sata_pins: sata-pins {
   rockchip,pins =

    <0 22 13 &pcfg_pull_none>,

    <0 28 13 &pcfg_pull_none>,

    <0 29 13 &pcfg_pull_none>;
  };
 };

 sata0 {
  /omit-if-no-ref/
  sata0m0_pins: sata0m0-pins {
   rockchip,pins =

    <4 14 6 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  sata0m1_pins: sata0m1-pins {
   rockchip,pins =

    <1 11 6 &pcfg_pull_none>;
  };
 };

 sata1 {
  /omit-if-no-ref/
  sata1m0_pins: sata1m0-pins {
   rockchip,pins =

    <4 13 6 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  sata1m1_pins: sata1m1-pins {
   rockchip,pins =

    <1 1 6 &pcfg_pull_none>;
  };
 };

 sata2 {
  /omit-if-no-ref/
  sata2m0_pins: sata2m0-pins {
   rockchip,pins =

    <4 9 6 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  sata2m1_pins: sata2m1-pins {
   rockchip,pins =

    <1 15 6 &pcfg_pull_none>;
  };
 };

 sdio {
  /omit-if-no-ref/
  sdiom1_pins: sdiom1-pins {
   rockchip,pins =

    <3 5 2 &pcfg_pull_none>,

    <3 4 2 &pcfg_pull_none>,

    <3 0 2 &pcfg_pull_none>,

    <3 1 2 &pcfg_pull_none>,

    <3 2 2 &pcfg_pull_none>,

    <3 3 2 &pcfg_pull_none>;
  };
 };

 sdmmc {
  /omit-if-no-ref/
  sdmmc_bus4: sdmmc-bus4 {
   rockchip,pins =

    <4 24 1 &pcfg_pull_up_drv_level_2>,

    <4 25 1 &pcfg_pull_up_drv_level_2>,

    <4 26 1 &pcfg_pull_up_drv_level_2>,

    <4 27 1 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  sdmmc_clk: sdmmc-clk {
   rockchip,pins =

    <4 29 1 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  sdmmc_cmd: sdmmc-cmd {
   rockchip,pins =

    <4 28 1 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  sdmmc_det: sdmmc-det {
   rockchip,pins =

    <0 4 1 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  sdmmc_pwren: sdmmc-pwren {
   rockchip,pins =

    <0 5 2 &pcfg_pull_none>;
  };
 };

 spdif0 {
  /omit-if-no-ref/
  spdif0m0_tx: spdif0m0-tx {
   rockchip,pins =

    <1 14 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  spdif0m1_tx: spdif0m1-tx {
   rockchip,pins =

    <4 12 6 &pcfg_pull_none>;
  };
 };

 spdif1 {
  /omit-if-no-ref/
  spdif1m0_tx: spdif1m0-tx {
   rockchip,pins =

    <1 15 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  spdif1m1_tx: spdif1m1-tx {
   rockchip,pins =

    <4 9 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  spdif1m2_tx: spdif1m2-tx {
   rockchip,pins =

    <4 17 3 &pcfg_pull_none>;
  };
 };

 spi0 {
  /omit-if-no-ref/
  spi0m0_pins: spi0m0-pins {
   rockchip,pins =

    <0 22 8 &pcfg_pull_up_drv_level_1>,

    <0 23 8 &pcfg_pull_up_drv_level_1>,

    <0 16 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi0m0_cs0: spi0m0-cs0 {
   rockchip,pins =

    <0 25 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi0m0_cs1: spi0m0-cs1 {
   rockchip,pins =

    <0 15 8 &pcfg_pull_up_drv_level_1>;
  };
  /omit-if-no-ref/
  spi0m1_pins: spi0m1-pins {
   rockchip,pins =

    <4 2 8 &pcfg_pull_up_drv_level_1>,

    <4 0 8 &pcfg_pull_up_drv_level_1>,

    <4 1 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi0m1_cs0: spi0m1-cs0 {
   rockchip,pins =

    <4 10 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi0m1_cs1: spi0m1-cs1 {
   rockchip,pins =

    <4 9 8 &pcfg_pull_up_drv_level_1>;
  };
  /omit-if-no-ref/
  spi0m2_pins: spi0m2-pins {
   rockchip,pins =

    <1 11 8 &pcfg_pull_up_drv_level_1>,

    <1 9 8 &pcfg_pull_up_drv_level_1>,

    <1 10 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi0m2_cs0: spi0m2-cs0 {
   rockchip,pins =

    <1 12 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi0m2_cs1: spi0m2-cs1 {
   rockchip,pins =

    <1 13 8 &pcfg_pull_up_drv_level_1>;
  };
  /omit-if-no-ref/
  spi0m3_pins: spi0m3-pins {
   rockchip,pins =

    <3 27 8 &pcfg_pull_up_drv_level_1>,

    <3 25 8 &pcfg_pull_up_drv_level_1>,

    <3 26 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi0m3_cs0: spi0m3-cs0 {
   rockchip,pins =

    <3 28 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi0m3_cs1: spi0m3-cs1 {
   rockchip,pins =

    <3 29 8 &pcfg_pull_up_drv_level_1>;
  };
 };

 spi1 {
  /omit-if-no-ref/
  spi1m1_pins: spi1m1-pins {
   rockchip,pins =

    <3 17 8 &pcfg_pull_up_drv_level_1>,

    <3 16 8 &pcfg_pull_up_drv_level_1>,

    <3 15 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi1m1_cs0: spi1m1-cs0 {
   rockchip,pins =

    <3 18 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi1m1_cs1: spi1m1-cs1 {
   rockchip,pins =

    <3 19 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi1m2_pins: spi1m2-pins {
   rockchip,pins =

    <1 26 8 &pcfg_pull_up_drv_level_1>,

    <1 24 8 &pcfg_pull_up_drv_level_1>,

    <1 25 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi1m2_cs0: spi1m2-cs0 {
   rockchip,pins =

    <1 27 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi1m2_cs1: spi1m2-cs1 {
   rockchip,pins =

    <1 29 8 &pcfg_pull_up_drv_level_1>;
  };
 };

 spi2 {
  /omit-if-no-ref/
  spi2m0_pins: spi2m0-pins {
   rockchip,pins =

    <1 6 8 &pcfg_pull_up_drv_level_1>,

    <1 4 8 &pcfg_pull_up_drv_level_1>,

    <1 5 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi2m0_cs0: spi2m0-cs0 {
   rockchip,pins =

    <1 7 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi2m0_cs1: spi2m0-cs1 {
   rockchip,pins =

    <1 8 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi2m1_pins: spi2m1-pins {
   rockchip,pins =

    <4 6 8 &pcfg_pull_up_drv_level_1>,

    <4 4 8 &pcfg_pull_up_drv_level_1>,

    <4 5 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi2m1_cs0: spi2m1-cs0 {
   rockchip,pins =

    <4 7 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi2m1_cs1: spi2m1-cs1 {
   rockchip,pins =

    <4 8 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi2m2_pins: spi2m2-pins {
   rockchip,pins =

    <0 5 1 &pcfg_pull_up_drv_level_1>,

    <0 11 1 &pcfg_pull_up_drv_level_1>,

    <0 6 1 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi2m2_cs0: spi2m2-cs0 {
   rockchip,pins =

    <0 9 1 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi2m2_cs1: spi2m2-cs1 {
   rockchip,pins =

    <0 8 1 &pcfg_pull_up_drv_level_1>;
  };
 };

 spi3 {
  /omit-if-no-ref/
  spi3m1_pins: spi3m1-pins {
   rockchip,pins =

    <4 15 8 &pcfg_pull_up_drv_level_1>,

    <4 13 8 &pcfg_pull_up_drv_level_1>,

    <4 14 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi3m1_cs0: spi3m1-cs0 {
   rockchip,pins =

    <4 16 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi3m1_cs1: spi3m1-cs1 {
   rockchip,pins =

    <4 17 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi3m2_pins: spi3m2-pins {
   rockchip,pins =

    <0 27 8 &pcfg_pull_up_drv_level_1>,

    <0 24 8 &pcfg_pull_up_drv_level_1>,

    <0 26 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi3m2_cs0: spi3m2-cs0 {
   rockchip,pins =

    <0 28 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi3m2_cs1: spi3m2-cs1 {
   rockchip,pins =

    <0 29 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi3m3_pins: spi3m3-pins {
   rockchip,pins =

    <3 24 8 &pcfg_pull_up_drv_level_1>,

    <3 22 8 &pcfg_pull_up_drv_level_1>,

    <3 23 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi3m3_cs0: spi3m3-cs0 {
   rockchip,pins =

    <3 20 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi3m3_cs1: spi3m3-cs1 {
   rockchip,pins =

    <3 21 8 &pcfg_pull_up_drv_level_1>;
  };
 };

 spi4 {
  /omit-if-no-ref/
  spi4m0_pins: spi4m0-pins {
   rockchip,pins =

    <1 18 8 &pcfg_pull_up_drv_level_1>,

    <1 16 8 &pcfg_pull_up_drv_level_1>,

    <1 17 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi4m0_cs0: spi4m0-cs0 {
   rockchip,pins =

    <1 19 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi4m0_cs1: spi4m0-cs1 {
   rockchip,pins =

    <1 20 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi4m1_pins: spi4m1-pins {
   rockchip,pins =

    <3 2 8 &pcfg_pull_up_drv_level_1>,

    <3 0 8 &pcfg_pull_up_drv_level_1>,

    <3 1 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi4m1_cs0: spi4m1-cs0 {
   rockchip,pins =

    <3 3 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi4m1_cs1: spi4m1-cs1 {
   rockchip,pins =

    <3 4 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi4m2_pins: spi4m2-pins {
   rockchip,pins =

    <1 2 8 &pcfg_pull_up_drv_level_1>,

    <1 0 8 &pcfg_pull_up_drv_level_1>,

    <1 1 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi4m2_cs0: spi4m2-cs0 {
   rockchip,pins =

    <1 3 8 &pcfg_pull_up_drv_level_1>;
  };
 };

 tsadc {
  /omit-if-no-ref/
  tsadcm1_shut: tsadcm1-shut {
   rockchip,pins =

    <0 2 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  tsadc_shut: tsadc-shut {
   rockchip,pins =

    <0 1 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  tsadc_shut_org: tsadc-shut-org {
   rockchip,pins =

    <0 1 1 &pcfg_pull_none>;
  };
 };

 uart0 {
  /omit-if-no-ref/
  uart0m0_xfer: uart0m0-xfer {
   rockchip,pins =

    <0 20 4 &pcfg_pull_up>,

    <0 21 4 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart0m1_xfer: uart0m1-xfer {
   rockchip,pins =

    <0 8 4 &pcfg_pull_up>,

    <0 9 4 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart0m2_xfer: uart0m2-xfer {
   rockchip,pins =

    <4 4 10 &pcfg_pull_up>,

    <4 3 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart0_ctsn: uart0-ctsn {
   rockchip,pins =

    <0 25 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart0_rtsn: uart0-rtsn {
   rockchip,pins =

    <0 22 4 &pcfg_pull_none>;
  };
 };

 uart1 {
  /omit-if-no-ref/
  uart1m1_xfer: uart1m1-xfer {
   rockchip,pins =

    <1 15 10 &pcfg_pull_up>,

    <1 14 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart1m1_ctsn: uart1m1-ctsn {
   rockchip,pins =

    <1 31 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart1m1_rtsn: uart1m1-rtsn {
   rockchip,pins =

    <1 30 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart1m2_xfer: uart1m2-xfer {
   rockchip,pins =

    <0 26 10 &pcfg_pull_up>,

    <0 25 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart1m2_ctsn: uart1m2-ctsn {
   rockchip,pins =

    <0 24 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart1m2_rtsn: uart1m2-rtsn {
   rockchip,pins =

    <0 23 10 &pcfg_pull_none>;
  };
 };

 uart2 {
  /omit-if-no-ref/
  uart2m0_xfer: uart2m0-xfer {
   rockchip,pins =

    <0 14 10 &pcfg_pull_up>,

    <0 13 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart2m1_xfer: uart2m1-xfer {
   rockchip,pins =

    <4 25 10 &pcfg_pull_up>,

    <4 24 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart2m2_xfer: uart2m2-xfer {
   rockchip,pins =

    <3 10 10 &pcfg_pull_up>,

    <3 9 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart2_ctsn: uart2-ctsn {
   rockchip,pins =

    <3 12 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart2_rtsn: uart2-rtsn {
   rockchip,pins =

    <3 11 10 &pcfg_pull_none>;
  };
 };

 uart3 {
  /omit-if-no-ref/
  uart3m0_xfer: uart3m0-xfer {
   rockchip,pins =

    <1 16 10 &pcfg_pull_up>,

    <1 17 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart3m1_xfer: uart3m1-xfer {
   rockchip,pins =

    <3 14 10 &pcfg_pull_up>,

    <3 13 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart3m2_xfer: uart3m2-xfer {
   rockchip,pins =

    <4 6 10 &pcfg_pull_up>,

    <4 5 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart3_ctsn: uart3-ctsn {
   rockchip,pins =

    <1 19 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart3_rtsn: uart3-rtsn {
   rockchip,pins =

    <1 18 10 &pcfg_pull_none>;
  };
 };

 uart4 {
  /omit-if-no-ref/
  uart4m0_xfer: uart4m0-xfer {
   rockchip,pins =

    <1 27 10 &pcfg_pull_up>,

    <1 26 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart4m1_xfer: uart4m1-xfer {
   rockchip,pins =

    <3 24 10 &pcfg_pull_up>,

    <3 25 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart4m2_xfer: uart4m2-xfer {
   rockchip,pins =

    <1 10 10 &pcfg_pull_up>,

    <1 11 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart4_ctsn: uart4-ctsn {
   rockchip,pins =

    <1 23 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart4_rtsn: uart4-rtsn {
   rockchip,pins =

    <1 21 10 &pcfg_pull_none>;
  };
 };

 uart5 {
  /omit-if-no-ref/
  uart5m0_xfer: uart5m0-xfer {
   rockchip,pins =

    <4 28 10 &pcfg_pull_up>,

    <4 29 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart5m0_ctsn: uart5m0-ctsn {
   rockchip,pins =

    <4 26 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart5m0_rtsn: uart5m0-rtsn {
   rockchip,pins =

    <4 27 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart5m1_xfer: uart5m1-xfer {
   rockchip,pins =

    <3 21 10 &pcfg_pull_up>,

    <3 20 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart5m1_ctsn: uart5m1-ctsn {
   rockchip,pins =

    <2 2 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart5m1_rtsn: uart5m1-rtsn {
   rockchip,pins =

    <2 3 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart5m2_xfer: uart5m2-xfer {
   rockchip,pins =

    <2 28 10 &pcfg_pull_up>,

    <2 29 10 &pcfg_pull_up>;
  };
 };

 uart6 {
  /omit-if-no-ref/
  uart6m1_xfer: uart6m1-xfer {
   rockchip,pins =

    <1 0 10 &pcfg_pull_up>,

    <1 1 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart6m1_ctsn: uart6m1-ctsn {
   rockchip,pins =

    <1 3 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart6m1_rtsn: uart6m1-rtsn {
   rockchip,pins =

    <1 2 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart6m2_xfer: uart6m2-xfer {
   rockchip,pins =

    <1 25 10 &pcfg_pull_up>,

    <1 24 10 &pcfg_pull_up>;
  };
 };

 uart7 {
  /omit-if-no-ref/
  uart7m1_xfer: uart7m1-xfer {
   rockchip,pins =

    <3 17 10 &pcfg_pull_up>,

    <3 16 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart7m1_ctsn: uart7m1-ctsn {
   rockchip,pins =

    <3 19 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart7m1_rtsn: uart7m1-rtsn {
   rockchip,pins =

    <3 18 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart7m2_xfer: uart7m2-xfer {
   rockchip,pins =

    <1 12 10 &pcfg_pull_up>,

    <1 13 10 &pcfg_pull_up>;
  };
 };

 uart8 {
  /omit-if-no-ref/
  uart8m0_xfer: uart8m0-xfer {
   rockchip,pins =

    <4 9 10 &pcfg_pull_up>,

    <4 8 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart8m0_ctsn: uart8m0-ctsn {
   rockchip,pins =

    <4 11 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart8m0_rtsn: uart8m0-rtsn {
   rockchip,pins =

    <4 10 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart8m1_xfer: uart8m1-xfer {
   rockchip,pins =

    <3 3 10 &pcfg_pull_up>,

    <3 2 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart8m1_ctsn: uart8m1-ctsn {
   rockchip,pins =

    <3 5 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart8m1_rtsn: uart8m1-rtsn {
   rockchip,pins =

    <3 4 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart8_xfer: uart8-xfer {
   rockchip,pins =

    <4 9 10 &pcfg_pull_up>;
  };
 };

 uart9 {
  /omit-if-no-ref/
  uart9m0_xfer: uart9m0-xfer {
   rockchip,pins =

    <2 20 10 &pcfg_pull_up>,

    <2 18 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart9m1_xfer: uart9m1-xfer {
   rockchip,pins =

    <4 13 10 &pcfg_pull_up>,

    <4 12 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart9m1_ctsn: uart9m1-ctsn {
   rockchip,pins =

    <4 1 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart9m1_rtsn: uart9m1-rtsn {
   rockchip,pins =

    <4 0 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart9m2_xfer: uart9m2-xfer {
   rockchip,pins =

    <3 28 10 &pcfg_pull_up>,

    <3 29 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart9m2_ctsn: uart9m2-ctsn {
   rockchip,pins =

    <3 27 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart9m2_rtsn: uart9m2-rtsn {
   rockchip,pins =

    <3 26 10 &pcfg_pull_none>;
  };
 };

 vop {
  /omit-if-no-ref/
  vop_pins: vop-pins {
   rockchip,pins =

    <1 2 1 &pcfg_pull_none>;
  };
 };
};




&pinctrl {
 bt656 {
  /omit-if-no-ref/
  bt656_pins: bt656-pins {
   rockchip,pins =

    <4 8 2 &pcfg_pull_none_drv_level_2>,

    <4 0 2 &pcfg_pull_none_drv_level_2>,

    <4 1 2 &pcfg_pull_none_drv_level_2>,

    <4 2 2 &pcfg_pull_none_drv_level_2>,

    <4 3 2 &pcfg_pull_none_drv_level_2>,

    <4 4 2 &pcfg_pull_none_drv_level_2>,

    <4 5 2 &pcfg_pull_none_drv_level_2>,

    <4 6 2 &pcfg_pull_none_drv_level_2>,

    <4 7 2 &pcfg_pull_none_drv_level_2>;
  };
 };

 gpio-func {
  /omit-if-no-ref/
  tsadc_gpio_func: tsadc-gpio-func {
   rockchip,pins =
    <0 1 0 &pcfg_pull_none>;
  };
 };
};
# 2888 "arch/arm64/boot/dts/rockchip/rk3588s.dtsi" 2
# 7 "arch/arm64/boot/dts/rockchip/rk3588.dtsi" 2
# 1 "arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi" 1






# 1 "arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi" 1





&pinctrl {
 /omit-if-no-ref/
 pcfg_pull_up: pcfg-pull-up {
  bias-pull-up;
 };

 /omit-if-no-ref/
 pcfg_pull_down: pcfg-pull-down {
  bias-pull-down;
 };

 /omit-if-no-ref/
 pcfg_pull_none: pcfg-pull-none {
  bias-disable;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
  bias-disable;
  drive-strength = <0>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
  bias-disable;
  drive-strength = <1>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
  bias-disable;
  drive-strength = <2>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
  bias-disable;
  drive-strength = <3>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 {
  bias-disable;
  drive-strength = <4>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 {
  bias-disable;
  drive-strength = <5>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 {
  bias-disable;
  drive-strength = <6>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 {
  bias-disable;
  drive-strength = <7>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 {
  bias-disable;
  drive-strength = <8>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 {
  bias-disable;
  drive-strength = <9>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 {
  bias-disable;
  drive-strength = <10>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 {
  bias-disable;
  drive-strength = <11>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 {
  bias-disable;
  drive-strength = <12>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 {
  bias-disable;
  drive-strength = <13>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 {
  bias-disable;
  drive-strength = <14>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 {
  bias-disable;
  drive-strength = <15>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 {
  bias-pull-up;
  drive-strength = <0>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 {
  bias-pull-up;
  drive-strength = <1>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 {
  bias-pull-up;
  drive-strength = <2>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 {
  bias-pull-up;
  drive-strength = <3>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 {
  bias-pull-up;
  drive-strength = <4>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 {
  bias-pull-up;
  drive-strength = <5>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 {
  bias-pull-up;
  drive-strength = <6>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 {
  bias-pull-up;
  drive-strength = <7>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 {
  bias-pull-up;
  drive-strength = <8>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 {
  bias-pull-up;
  drive-strength = <9>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 {
  bias-pull-up;
  drive-strength = <10>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 {
  bias-pull-up;
  drive-strength = <11>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 {
  bias-pull-up;
  drive-strength = <12>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 {
  bias-pull-up;
  drive-strength = <13>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 {
  bias-pull-up;
  drive-strength = <14>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 {
  bias-pull-up;
  drive-strength = <15>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 {
  bias-pull-down;
  drive-strength = <0>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 {
  bias-pull-down;
  drive-strength = <1>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 {
  bias-pull-down;
  drive-strength = <2>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 {
  bias-pull-down;
  drive-strength = <3>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 {
  bias-pull-down;
  drive-strength = <4>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 {
  bias-pull-down;
  drive-strength = <5>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 {
  bias-pull-down;
  drive-strength = <6>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 {
  bias-pull-down;
  drive-strength = <7>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 {
  bias-pull-down;
  drive-strength = <8>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 {
  bias-pull-down;
  drive-strength = <9>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 {
  bias-pull-down;
  drive-strength = <10>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 {
  bias-pull-down;
  drive-strength = <11>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 {
  bias-pull-down;
  drive-strength = <12>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 {
  bias-pull-down;
  drive-strength = <13>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 {
  bias-pull-down;
  drive-strength = <14>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 {
  bias-pull-down;
  drive-strength = <15>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_smt: pcfg-pull-up-smt {
  bias-pull-up;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_pull_down_smt: pcfg-pull-down-smt {
  bias-pull-down;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_pull_none_smt: pcfg-pull-none-smt {
  bias-disable;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt {
  bias-disable;
  drive-strength = <0>;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_output_high: pcfg-output-high {
  output-high;
 };

 /omit-if-no-ref/
 pcfg_output_low: pcfg-output-low {
  output-low;
 };
};
# 8 "arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi" 2





&pinctrl {
 clk32k {
  /omit-if-no-ref/
  clk32k_out1: clk32k-out1 {
   rockchip,pins =

    <2 21 1 &pcfg_pull_none>;
  };

 };

 eth0 {
  /omit-if-no-ref/
  eth0_pins: eth0-pins {
   rockchip,pins =

    <2 19 1 &pcfg_pull_none>;
  };

 };

 fspi {
  /omit-if-no-ref/
  fspim1_pins: fspim1-pins {
   rockchip,pins =

    <2 11 3 &pcfg_pull_up_drv_level_2>,

    <2 12 3 &pcfg_pull_up_drv_level_2>,

    <2 6 3 &pcfg_pull_up_drv_level_2>,

    <2 7 3 &pcfg_pull_up_drv_level_2>,

    <2 8 3 &pcfg_pull_up_drv_level_2>,

    <2 9 3 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  fspim1_cs1: fspim1-cs1 {
   rockchip,pins =

    <2 13 3 &pcfg_pull_up_drv_level_2>;
  };
 };

 gmac0 {
  /omit-if-no-ref/
  gmac0_miim: gmac0-miim {
   rockchip,pins =

    <4 20 1 &pcfg_pull_none>,

    <4 21 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac0_clkinout: gmac0-clkinout {
   rockchip,pins =

    <4 19 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac0_rx_bus2: gmac0-rx-bus2 {
   rockchip,pins =

    <2 17 1 &pcfg_pull_none>,

    <2 18 1 &pcfg_pull_none>,

    <4 18 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac0_tx_bus2: gmac0-tx-bus2 {
   rockchip,pins =

    <2 14 1 &pcfg_pull_none>,

    <2 15 1 &pcfg_pull_none>,

    <2 16 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac0_rgmii_clk: gmac0-rgmii-clk {
   rockchip,pins =

    <2 8 1 &pcfg_pull_none>,

    <2 11 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac0_rgmii_bus: gmac0-rgmii-bus {
   rockchip,pins =

    <2 6 1 &pcfg_pull_none>,

    <2 7 1 &pcfg_pull_none>,

    <2 9 1 &pcfg_pull_none>,

    <2 10 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac0_ppsclk: gmac0-ppsclk {
   rockchip,pins =

    <2 20 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac0_ppstring: gmac0-ppstring {
   rockchip,pins =

    <2 13 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac0_ptp_refclk: gmac0-ptp-refclk {
   rockchip,pins =

    <2 12 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac0_txer: gmac0-txer {
   rockchip,pins =

    <4 22 1 &pcfg_pull_none>;
  };

 };

 hdmi {
  /omit-if-no-ref/
  hdmim0_tx1_cec: hdmim0-tx1-cec {
   rockchip,pins =

    <2 20 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim0_tx1_scl: hdmim0-tx1-scl {
   rockchip,pins =

    <2 13 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim0_tx1_sda: hdmim0-tx1-sda {
   rockchip,pins =

    <2 12 4 &pcfg_pull_none>;
  };
 };

 i2c0 {
  /omit-if-no-ref/
  i2c0m1_xfer: i2c0m1-xfer {
   rockchip,pins =

    <4 21 9 &pcfg_pull_none_smt>,

    <4 22 9 &pcfg_pull_none_smt>;
  };
 };

 i2c2 {
  /omit-if-no-ref/
  i2c2m1_xfer: i2c2m1-xfer {
   rockchip,pins =

    <2 17 9 &pcfg_pull_none_smt>,

    <2 16 9 &pcfg_pull_none_smt>;
  };
 };

 i2c3 {
  /omit-if-no-ref/
  i2c3m3_xfer: i2c3m3-xfer {
   rockchip,pins =

    <2 10 9 &pcfg_pull_none_smt>,

    <2 11 9 &pcfg_pull_none_smt>;
  };
 };

 i2c4 {
  /omit-if-no-ref/
  i2c4m1_xfer: i2c4m1-xfer {
   rockchip,pins =

    <2 13 9 &pcfg_pull_none_smt>,

    <2 12 9 &pcfg_pull_none_smt>;
  };
 };

 i2c5 {
  /omit-if-no-ref/
  i2c5m4_xfer: i2c5m4-xfer {
   rockchip,pins =

    <2 14 9 &pcfg_pull_none_smt>,

    <2 15 9 &pcfg_pull_none_smt>;
  };
 };

 i2c6 {
  /omit-if-no-ref/
  i2c6m2_xfer: i2c6m2-xfer {
   rockchip,pins =

    <2 19 9 &pcfg_pull_none_smt>,

    <2 18 9 &pcfg_pull_none_smt>;
  };
 };

 i2c7 {
  /omit-if-no-ref/
  i2c7m1_xfer: i2c7m1-xfer {
   rockchip,pins =

    <4 19 9 &pcfg_pull_none_smt>,

    <4 20 9 &pcfg_pull_none_smt>;
  };
 };

 i2c8 {
  /omit-if-no-ref/
  i2c8m1_xfer: i2c8m1-xfer {
   rockchip,pins =

    <2 8 9 &pcfg_pull_none_smt>,

    <2 9 9 &pcfg_pull_none_smt>;
  };
 };

 i2s2 {
  /omit-if-no-ref/
  i2s2m0_lrck: i2s2m0-lrck {
   rockchip,pins =

    <2 16 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m0_mclk: i2s2m0-mclk {
   rockchip,pins =

    <2 14 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m0_sclk: i2s2m0-sclk {
   rockchip,pins =

    <2 15 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m0_sdi: i2s2m0-sdi {
   rockchip,pins =

    <2 19 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m0_sdo: i2s2m0-sdo {
   rockchip,pins =

    <4 19 2 &pcfg_pull_none>;
  };
 };

 pwm2 {
  /omit-if-no-ref/
  pwm2m2_pins: pwm2m2-pins {
   rockchip,pins =

    <4 18 11 &pcfg_pull_none>;
  };
 };

 pwm4 {
  /omit-if-no-ref/
  pwm4m1_pins: pwm4m1-pins {
   rockchip,pins =

    <4 19 11 &pcfg_pull_none>;
  };
 };

 pwm5 {
  /omit-if-no-ref/
  pwm5m2_pins: pwm5m2-pins {
   rockchip,pins =

    <4 20 11 &pcfg_pull_none>;
  };
 };

 pwm6 {
  /omit-if-no-ref/
  pwm6m2_pins: pwm6m2-pins {
   rockchip,pins =

    <4 21 11 &pcfg_pull_none>;
  };
 };

 pwm7 {
  /omit-if-no-ref/
  pwm7m3_pins: pwm7m3-pins {
   rockchip,pins =

    <4 22 11 &pcfg_pull_none>;
  };
 };

 sdio {
  /omit-if-no-ref/
  sdiom0_pins: sdiom0-pins {
   rockchip,pins =

    <2 11 2 &pcfg_pull_none>,

    <2 10 2 &pcfg_pull_none>,

    <2 6 2 &pcfg_pull_none>,

    <2 7 2 &pcfg_pull_none>,

    <2 8 2 &pcfg_pull_none>,

    <2 9 2 &pcfg_pull_none>;
  };
 };

 spi1 {
  /omit-if-no-ref/
  spi1m0_pins: spi1m0-pins {
   rockchip,pins =

    <2 16 8 &pcfg_pull_up_drv_level_1>,

    <2 17 8 &pcfg_pull_up_drv_level_1>,

    <2 18 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi1m0_cs0: spi1m0-cs0 {
   rockchip,pins =

    <2 19 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi1m0_cs1: spi1m0-cs1 {
   rockchip,pins =

    <2 20 8 &pcfg_pull_up_drv_level_1>;
  };
 };

 spi3 {
  /omit-if-no-ref/
  spi3m0_pins: spi3m0-pins {
   rockchip,pins =

    <4 22 8 &pcfg_pull_up_drv_level_1>,

    <4 20 8 &pcfg_pull_up_drv_level_1>,

    <4 21 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi3m0_cs0: spi3m0-cs0 {
   rockchip,pins =

    <4 18 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi3m0_cs1: spi3m0-cs1 {
   rockchip,pins =

    <4 19 8 &pcfg_pull_up_drv_level_1>;
  };
 };

 uart1 {
  /omit-if-no-ref/
  uart1m0_xfer: uart1m0-xfer {
   rockchip,pins =

    <2 14 10 &pcfg_pull_up>,

    <2 15 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart1m0_ctsn: uart1m0-ctsn {
   rockchip,pins =

    <2 17 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart1m0_rtsn: uart1m0-rtsn {
   rockchip,pins =

    <2 16 10 &pcfg_pull_none>;
  };
 };

 uart6 {
  /omit-if-no-ref/
  uart6m0_xfer: uart6m0-xfer {
   rockchip,pins =

    <2 6 10 &pcfg_pull_up>,

    <2 7 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart6m0_ctsn: uart6m0-ctsn {
   rockchip,pins =

    <2 9 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart6m0_rtsn: uart6m0-rtsn {
   rockchip,pins =

    <2 8 10 &pcfg_pull_none>;
  };
 };

 uart7 {
  /omit-if-no-ref/
  uart7m0_xfer: uart7m0-xfer {
   rockchip,pins =

    <2 12 10 &pcfg_pull_up>,

    <2 13 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart7m0_ctsn: uart7m0-ctsn {
   rockchip,pins =

    <4 22 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart7m0_rtsn: uart7m0-rtsn {
   rockchip,pins =

    <4 18 10 &pcfg_pull_none>;
  };
 };

 uart9 {
  /omit-if-no-ref/
  uart9m0_xfer: uart9m0-xfer {
   rockchip,pins =

    <2 20 10 &pcfg_pull_up>,

    <2 18 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart9m0_ctsn: uart9m0-ctsn {
   rockchip,pins =

    <4 21 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart9m0_rtsn: uart9m0-rtsn {
   rockchip,pins =

    <4 20 10 &pcfg_pull_none>;
  };
 };
};
# 8 "arch/arm64/boot/dts/rockchip/rk3588.dtsi" 2

/ {
 usb_host1_xhci: usb@fc400000 {
  compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
  reg = <0x0 0xfc400000 0x0 0x400000>;
  interrupts = <0 221 4 0>;
  clocks = <&cru 407>, <&cru 406>,
    <&cru 405>;
  clock-names = "ref_clk", "suspend_clk", "bus_clk";
  dr_mode = "host";
  phys = <&u2phy1_otg>, <&usbdp_phy1_u3>;
  phy-names = "usb2-phy", "usb3-phy";
  phy_type = "utmi_wide";
  power-domains = <&power 31>;
  resets = <&cru 339>;
  snps,dis_enblslpm_quirk;
  snps,dis-u2-freeclk-exists-quirk;
  snps,dis-del-phy-power-chg-quirk;
  snps,dis-tx-ipgap-linecheck-quirk;
  status = "disabled";
 };

 pcie30_phy_grf: syscon@fd5b8000 {
  compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
  reg = <0x0 0xfd5b8000 0x0 0x10000>;
 };

 pipe_phy1_grf: syscon@fd5c0000 {
  compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
  reg = <0x0 0xfd5c0000 0x0 0x100>;
 };

 usbdpphy1_grf: syscon@fd5cc000 {
  compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
  reg = <0x0 0xfd5cc000 0x0 0x4000>;
 };

 usb2phy1_grf: syscon@fd5d4000 {
  compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
        "simple-mfd";
  reg = <0x0 0xfd5d4000 0x0 0x4000>;
  #address-cells = <1>;
  #size-cells = <1>;

  u2phy1: usb2-phy@4000 {
   compatible = "rockchip,rk3588-usb2phy";
   reg = <0x4000 0x10>;
   interrupts = <0 394 4 0>;
   resets = <&cru 622>, <&cru 542>;
   reset-names = "phy", "apb";
   clocks = <&cru 672>;
   clock-names = "phyclk";
   clock-output-names = "usb480m_phy1";
   #clock-cells = <0>;
   status = "disabled";

   u2phy1_otg: otg-port {
    #phy-cells = <0>;
    status = "disabled";
   };
  };
 };

 i2s8_8ch: i2s@fddc8000 {
  compatible = "rockchip,rk3588-i2s-tdm";
  reg = <0x0 0xfddc8000 0x0 0x1000>;
  interrupts = <0 188 4 0>;
  clocks = <&cru 497>, <&cru 497>, <&cru 494>;
  clock-names = "mclk_tx", "mclk_rx", "hclk";
  assigned-clocks = <&cru 495>;
  assigned-clock-parents = <&cru 4>;
  dmas = <&dmac2 22>;
  dma-names = "tx";
  power-domains = <&power 25>;
  resets = <&cru 442>;
  reset-names = "tx-m";
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 i2s6_8ch: i2s@fddf4000 {
  compatible = "rockchip,rk3588-i2s-tdm";
  reg = <0x0 0xfddf4000 0x0 0x1000>;
  interrupts = <0 186 4 0>;
  clocks = <&cru 569>, <&cru 569>, <&cru 575>;
  clock-names = "mclk_tx", "mclk_rx", "hclk";
  assigned-clocks = <&cru 566>;
  assigned-clock-parents = <&cru 4>;
  dmas = <&dmac2 4>;
  dma-names = "tx";
  power-domains = <&power 26>;
  resets = <&cru 474>;
  reset-names = "tx-m";
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 i2s7_8ch: i2s@fddf8000 {
  compatible = "rockchip,rk3588-i2s-tdm";
  reg = <0x0 0xfddf8000 0x0 0x1000>;
  interrupts = <0 187 4 0>;
  clocks = <&cru 555>, <&cru 555>, <&cru 551>;
  clock-names = "mclk_tx", "mclk_rx", "hclk";
  assigned-clocks = <&cru 552>;
  assigned-clock-parents = <&cru 4>;
  dmas = <&dmac2 21>;
  dma-names = "rx";
  power-domains = <&power 26>;
  resets = <&cru 455>;
  reset-names = "rx-m";
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 i2s10_8ch: i2s@fde00000 {
  compatible = "rockchip,rk3588-i2s-tdm";
  reg = <0x0 0xfde00000 0x0 0x1000>;
  interrupts = <0 190 4 0>;
  clocks = <&cru 550>, <&cru 550>, <&cru 546>;
  clock-names = "mclk_tx", "mclk_rx", "hclk";
  assigned-clocks = <&cru 547>;
  assigned-clock-parents = <&cru 4>;
  dmas = <&dmac2 24>;
  dma-names = "rx";
  power-domains = <&power 26>;
  resets = <&cru 494>;
  reset-names = "rx-m";
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 pcie3x4: pcie@fe150000 {
  compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
  #address-cells = <3>;
  #size-cells = <2>;
  bus-range = <0x00 0x0f>;
  clocks = <&cru 320>, <&cru 325>,
    <&cru 315>, <&cru 330>,
    <&cru 335>, <&cru 372>;
  clock-names = "aclk_mst", "aclk_slv",
         "aclk_dbi", "pclk",
         "aux", "pipe";
  device_type = "pci";
  interrupts = <0 263 4 0>,
        <0 262 4 0>,
        <0 261 4 0>,
        <0 260 4 0>,
        <0 259 4 0>;
  interrupt-names = "sys", "pmc", "msg", "legacy", "err";
  #interrupt-cells = <1>;
  interrupt-map-mask = <0 0 0 7>;
  interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
    <0 0 0 2 &pcie3x4_intc 1>,
    <0 0 0 3 &pcie3x4_intc 2>,
    <0 0 0 4 &pcie3x4_intc 3>;
  linux,pci-domain = <0>;
  max-link-speed = <3>;
  msi-map = <0x0000 &its1 0x0000 0x1000>;
  num-lanes = <4>;
  phys = <&pcie30phy>;
  phy-names = "pcie-phy";
  power-domains = <&power 34>;
  ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
    <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
    <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
  reg = <0xa 0x40000000 0x0 0x00400000>,
        <0x0 0xfe150000 0x0 0x00010000>,
        <0x0 0xf0000000 0x0 0x00100000>;
  reg-names = "dbi", "apb", "config";
  resets = <&cru 294>, <&cru 299>;
  reset-names = "pwr", "pipe";
  status = "disabled";

  pcie3x4_intc: legacy-interrupt-controller {
   interrupt-controller;
   #address-cells = <0>;
   #interrupt-cells = <1>;
   interrupt-parent = <&gic>;
   interrupts = <0 260 1 0>;
  };
 };

 pcie3x2: pcie@fe160000 {
  compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
  #address-cells = <3>;
  #size-cells = <2>;
  bus-range = <0x10 0x1f>;
  clocks = <&cru 321>, <&cru 326>,
    <&cru 316>, <&cru 331>,
    <&cru 336>, <&cru 373>;
  clock-names = "aclk_mst", "aclk_slv",
         "aclk_dbi", "pclk",
         "aux", "pipe";
  device_type = "pci";
  interrupts = <0 258 4 0>,
        <0 257 4 0>,
        <0 256 4 0>,
        <0 255 4 0>,
        <0 254 4 0>;
  interrupt-names = "sys", "pmc", "msg", "legacy", "err";
  #interrupt-cells = <1>;
  interrupt-map-mask = <0 0 0 7>;
  interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
    <0 0 0 2 &pcie3x2_intc 1>,
    <0 0 0 3 &pcie3x2_intc 2>,
    <0 0 0 4 &pcie3x2_intc 3>;
  linux,pci-domain = <1>;
  max-link-speed = <3>;
  msi-map = <0x1000 &its1 0x1000 0x1000>;
  num-lanes = <2>;
  phys = <&pcie30phy>;
  phy-names = "pcie-phy";
  power-domains = <&power 34>;
  ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
    <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
    <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
  reg = <0xa 0x40400000 0x0 0x00400000>,
        <0x0 0xfe160000 0x0 0x00010000>,
        <0x0 0xf1000000 0x0 0x00100000>;
  reg-names = "dbi", "apb", "config";
  resets = <&cru 295>, <&cru 300>;
  reset-names = "pwr", "pipe";
  status = "disabled";

  pcie3x2_intc: legacy-interrupt-controller {
   interrupt-controller;
   #address-cells = <0>;
   #interrupt-cells = <1>;
   interrupt-parent = <&gic>;
   interrupts = <0 255 1 0>;
  };
 };

 pcie2x1l0: pcie@fe170000 {
  compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
  bus-range = <0x20 0x2f>;
  clocks = <&cru 322>, <&cru 327>,
    <&cru 317>, <&cru 332>,
    <&cru 337>, <&cru 687>;
  clock-names = "aclk_mst", "aclk_slv",
         "aclk_dbi", "pclk",
         "aux", "pipe";
  device_type = "pci";
  interrupts = <0 243 4 0>,
        <0 242 4 0>,
        <0 241 4 0>,
        <0 240 4 0>,
        <0 239 4 0>;
  interrupt-names = "sys", "pmc", "msg", "legacy", "err";
  #interrupt-cells = <1>;
  interrupt-map-mask = <0 0 0 7>;
  interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
    <0 0 0 2 &pcie2x1l0_intc 1>,
    <0 0 0 3 &pcie2x1l0_intc 2>,
    <0 0 0 4 &pcie2x1l0_intc 3>;
  linux,pci-domain = <2>;
  max-link-speed = <2>;
  msi-map = <0x2000 &its0 0x2000 0x1000>;
  num-lanes = <1>;
  phys = <&combphy1_ps 2>;
  phy-names = "pcie-phy";
  power-domains = <&power 34>;
  ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
    <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
    <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;
  reg = <0xa 0x40800000 0x0 0x00400000>,
        <0x0 0xfe170000 0x0 0x00010000>,
        <0x0 0xf2000000 0x0 0x00100000>;
  reg-names = "dbi", "apb", "config";
  resets = <&cru 296>, <&cru 301>;
  reset-names = "pwr", "pipe";
  #address-cells = <3>;
  #size-cells = <2>;
  status = "disabled";

  pcie2x1l0_intc: legacy-interrupt-controller {
   interrupt-controller;
   #address-cells = <0>;
   #interrupt-cells = <1>;
   interrupt-parent = <&gic>;
   interrupts = <0 240 1 0>;
  };
 };

 gmac0: ethernet@fe1b0000 {
  compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
  reg = <0x0 0xfe1b0000 0x0 0x10000>;
  interrupts = <0 227 4 0>,
        <0 226 4 0>;
  interrupt-names = "macirq", "eth_wake_irq";
  clocks = <&cru 310>, <&cru 311>,
    <&cru 344>, <&cru 349>,
    <&cru 308>;
  clock-names = "stmmaceth", "clk_mac_ref",
         "pclk_mac", "aclk_mac",
         "ptp_ref";
  power-domains = <&power 33>;
  resets = <&cru 291>;
  reset-names = "stmmaceth";
  rockchip,grf = <&sys_grf>;
  rockchip,php-grf = <&php_grf>;
  snps,axi-config = <&gmac0_stmmac_axi_setup>;
  snps,mixed-burst;
  snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
  snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
  snps,tso;
  status = "disabled";

  mdio0: mdio {
   compatible = "snps,dwmac-mdio";
   #address-cells = <0x1>;
   #size-cells = <0x0>;
  };

  gmac0_stmmac_axi_setup: stmmac-axi-config {
   snps,blen = <0 0 0 0 16 8 4>;
   snps,wr_osr_lmt = <4>;
   snps,rd_osr_lmt = <8>;
  };

  gmac0_mtl_rx_setup: rx-queues-config {
   snps,rx-queues-to-use = <2>;
   queue0 {};
   queue1 {};
  };

  gmac0_mtl_tx_setup: tx-queues-config {
   snps,tx-queues-to-use = <2>;
   queue0 {};
   queue1 {};
  };
 };

 sata1: sata@fe220000 {
  compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
  reg = <0 0xfe220000 0 0x1000>;
  interrupts = <0 274 4 0>;
  clocks = <&cru 355>, <&cru 352>,
    <&cru 358>, <&cru 341>,
    <&cru 368>;
  clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
  ports-implemented = <0x1>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";

  sata-port@0 {
   reg = <0>;
   hba-port-cap = <(1 << 22)>;
   phys = <&combphy1_ps 1>;
   phy-names = "sata-phy";
   snps,rx-ts-max = <32>;
   snps,tx-ts-max = <32>;
  };
 };

 usbdp_phy1: phy@fed90000 {
  compatible = "rockchip,rk3588-usbdp-phy";
  reg = <0x0 0xfed90000 0x0 0x10000>;
  rockchip,u2phy-grf = <&usb2phy1_grf>;
  rockchip,usb-grf = <&usb_grf>;
  rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
  rockchip,vo-grf = <&vo0_grf>;
  clocks = <&cru 673>,
    <&cru 621>,
    <&cru 599>,
    <&u2phy1>;
  clock-names = "refclk", "immortal", "pclk", "utmi";
  resets = <&cru 15>,
    <&cru 16>,
    <&cru 17>,
    <&cru 18>,
    <&cru 537>;
  reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
  status = "disabled";

  usbdp_phy1_dp: dp-port {
   #phy-cells = <0>;
   status = "disabled";
  };

  usbdp_phy1_u3: usb3-port {
   #phy-cells = <0>;
   status = "disabled";
  };
 };

 combphy1_ps: phy@fee10000 {
  compatible = "rockchip,rk3588-naneng-combphy";
  reg = <0x0 0xfee10000 0x0 0x100>;
  clocks = <&cru 681>, <&cru 375>,
    <&cru 343>;
  clock-names = "ref", "apb", "pipe";
  assigned-clocks = <&cru 681>;
  assigned-clock-rates = <100000000>;
  #phy-cells = <1>;
  resets = <&cru 573>, <&cru 580>;
  reset-names = "phy", "apb";
  rockchip,pipe-grf = <&php_grf>;
  rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
  status = "disabled";
 };

 pcie30phy: phy@fee80000 {
  compatible = "rockchip,rk3588-pcie3-phy";
  reg = <0x0 0xfee80000 0x0 0x20000>;
  #phy-cells = <0>;
  clocks = <&cru 377>;
  clock-names = "pclk";
  resets = <&cru 584>;
  reset-names = "phy";
  rockchip,pipe-grf = <&php_grf>;
  rockchip,phy-grf = <&pcie30_phy_grf>;
  status = "disabled";
 };
};
# 8 "arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts" 2
# 1 "arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a.dtsi" 1





/ {
 compatible = "edgeble,neural-compute-module-6a", "rockchip,rk3588";

 aliases {
  mmc0 = &sdhci;
 };

 vcc12v_dcin: vcc12v-dcin-regulator {
  compatible = "regulator-fixed";
  regulator-name = "vcc12v_dcin";
  regulator-always-on;
  regulator-boot-on;
  regulator-min-microvolt = <12000000>;
  regulator-max-microvolt = <12000000>;
 };
};

&sdhci {
 bus-width = <8>;
 no-sdio;
 no-sd;
 non-removable;
 mmc-hs400-1_8v;
 mmc-hs400-enhanced-strobe;
 status = "okay";
};
# 9 "arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts" 2

/ {
 model = "Edgeble Neu6A IO Board";
 compatible = "edgeble,neural-compute-module-6a-io",
       "edgeble,neural-compute-module-6a", "rockchip,rk3588";

 aliases {
  serial2 = &uart2;
 };

 chosen {
  stdout-path = "serial2:1500000n8";
 };
};

&uart2 {
 pinctrl-0 = <&uart2m0_xfer>;
 status = "okay";
};