# 0 "arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts"
# 0 "<built-in>"
# 0 "<command-line>"
# 1 "arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts"


/dts-v1/;

# 1 "./scripts/dtc/include-prefixes/dt-bindings/gpio/gpio.h" 1
# 6 "arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/pinctrl/rockchip.h" 1
# 7 "arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/soc/rockchip,vop2.h" 1
# 8 "arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts" 2
# 1 "arch/arm64/boot/dts/rockchip/rk3566.dtsi" 1


# 1 "arch/arm64/boot/dts/rockchip/rk356x.dtsi" 1





# 1 "./scripts/dtc/include-prefixes/dt-bindings/clock/rk3568-cru.h" 1
# 7 "arch/arm64/boot/dts/rockchip/rk356x.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h" 1
# 9 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h"
# 1 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/irq.h" 1
# 10 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h" 2
# 8 "arch/arm64/boot/dts/rockchip/rk356x.dtsi" 2

# 1 "./scripts/dtc/include-prefixes/dt-bindings/phy/phy.h" 1
# 10 "arch/arm64/boot/dts/rockchip/rk356x.dtsi" 2

# 1 "./scripts/dtc/include-prefixes/dt-bindings/power/rk3568-power.h" 1
# 12 "arch/arm64/boot/dts/rockchip/rk356x.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/soc/rockchip,boot-mode.h" 1
# 13 "arch/arm64/boot/dts/rockchip/rk356x.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/thermal/thermal.h" 1
# 14 "arch/arm64/boot/dts/rockchip/rk356x.dtsi" 2

/ {
 interrupt-parent = <&gic>;
 #address-cells = <2>;
 #size-cells = <2>;

 aliases {
  gpio0 = &gpio0;
  gpio1 = &gpio1;
  gpio2 = &gpio2;
  gpio3 = &gpio3;
  gpio4 = &gpio4;
  i2c0 = &i2c0;
  i2c1 = &i2c1;
  i2c2 = &i2c2;
  i2c3 = &i2c3;
  i2c4 = &i2c4;
  i2c5 = &i2c5;
  serial0 = &uart0;
  serial1 = &uart1;
  serial2 = &uart2;
  serial3 = &uart3;
  serial4 = &uart4;
  serial5 = &uart5;
  serial6 = &uart6;
  serial7 = &uart7;
  serial8 = &uart8;
  serial9 = &uart9;
  spi0 = &spi0;
  spi1 = &spi1;
  spi2 = &spi2;
  spi3 = &spi3;
 };

 cpus {
  #address-cells = <2>;
  #size-cells = <0>;

  cpu0: cpu@0 {
   device_type = "cpu";
   compatible = "arm,cortex-a55";
   reg = <0x0 0x0>;
   clocks = <&scmi_clk 0>;
   #cooling-cells = <2>;
   enable-method = "psci";
   operating-points-v2 = <&cpu0_opp_table>;
  };

  cpu1: cpu@100 {
   device_type = "cpu";
   compatible = "arm,cortex-a55";
   reg = <0x0 0x100>;
   #cooling-cells = <2>;
   enable-method = "psci";
   operating-points-v2 = <&cpu0_opp_table>;
  };

  cpu2: cpu@200 {
   device_type = "cpu";
   compatible = "arm,cortex-a55";
   reg = <0x0 0x200>;
   #cooling-cells = <2>;
   enable-method = "psci";
   operating-points-v2 = <&cpu0_opp_table>;
  };

  cpu3: cpu@300 {
   device_type = "cpu";
   compatible = "arm,cortex-a55";
   reg = <0x0 0x300>;
   #cooling-cells = <2>;
   enable-method = "psci";
   operating-points-v2 = <&cpu0_opp_table>;
  };
 };

 cpu0_opp_table: opp-table-0 {
  compatible = "operating-points-v2";
  opp-shared;

  opp-408000000 {
   opp-hz = /bits/ 64 <408000000>;
   opp-microvolt = <900000 900000 1150000>;
   clock-latency-ns = <40000>;
  };

  opp-600000000 {
   opp-hz = /bits/ 64 <600000000>;
   opp-microvolt = <900000 900000 1150000>;
  };

  opp-816000000 {
   opp-hz = /bits/ 64 <816000000>;
   opp-microvolt = <900000 900000 1150000>;
   opp-suspend;
  };

  opp-1104000000 {
   opp-hz = /bits/ 64 <1104000000>;
   opp-microvolt = <900000 900000 1150000>;
  };

  opp-1416000000 {
   opp-hz = /bits/ 64 <1416000000>;
   opp-microvolt = <900000 900000 1150000>;
  };

  opp-1608000000 {
   opp-hz = /bits/ 64 <1608000000>;
   opp-microvolt = <975000 975000 1150000>;
  };

  opp-1800000000 {
   opp-hz = /bits/ 64 <1800000000>;
   opp-microvolt = <1050000 1050000 1150000>;
  };
 };

 display_subsystem: display-subsystem {
  compatible = "rockchip,display-subsystem";
  ports = <&vop_out>;
 };

 firmware {
  scmi: scmi {
   compatible = "arm,scmi-smc";
   arm,smc-id = <0x82000010>;
   shmem = <&scmi_shmem>;
   #address-cells = <1>;
   #size-cells = <0>;

   scmi_clk: protocol@14 {
    reg = <0x14>;
    #clock-cells = <1>;
   };
  };
 };

 gpu_opp_table: opp-table-1 {
  compatible = "operating-points-v2";

  opp-200000000 {
   opp-hz = /bits/ 64 <200000000>;
   opp-microvolt = <825000>;
  };

  opp-300000000 {
   opp-hz = /bits/ 64 <300000000>;
   opp-microvolt = <825000>;
  };

  opp-400000000 {
   opp-hz = /bits/ 64 <400000000>;
   opp-microvolt = <825000>;
  };

  opp-600000000 {
   opp-hz = /bits/ 64 <600000000>;
   opp-microvolt = <825000>;
  };

  opp-700000000 {
   opp-hz = /bits/ 64 <700000000>;
   opp-microvolt = <900000>;
  };

  opp-800000000 {
   opp-hz = /bits/ 64 <800000000>;
   opp-microvolt = <1000000>;
  };
 };

 hdmi_sound: hdmi-sound {
  compatible = "simple-audio-card";
  simple-audio-card,name = "HDMI";
  simple-audio-card,format = "i2s";
  simple-audio-card,mclk-fs = <256>;
  status = "disabled";

  simple-audio-card,codec {
   sound-dai = <&hdmi>;
  };

  simple-audio-card,cpu {
   sound-dai = <&i2s0_8ch>;
  };
 };

 pmu {
  compatible = "arm,cortex-a55-pmu";
  interrupts = <0 228 4>,
        <0 229 4>,
        <0 230 4>,
        <0 231 4>;
  interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 };

 psci {
  compatible = "arm,psci-1.0";
  method = "smc";
 };

 timer {
  compatible = "arm,armv8-timer";
  interrupts = <1 13 4>,
        <1 14 4>,
        <1 11 4>,
        <1 10 4>;
  arm,no-tick-in-suspend;
 };

 xin24m: xin24m {
  compatible = "fixed-clock";
  clock-frequency = <24000000>;
  clock-output-names = "xin24m";
  #clock-cells = <0>;
 };

 xin32k: xin32k {
  compatible = "fixed-clock";
  clock-frequency = <32768>;
  clock-output-names = "xin32k";
  pinctrl-0 = <&clk32k_out0>;
  pinctrl-names = "default";
  #clock-cells = <0>;
 };

 sram@10f000 {
  compatible = "mmio-sram";
  reg = <0x0 0x0010f000 0x0 0x100>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0 0x0 0x0010f000 0x100>;

  scmi_shmem: sram@0 {
   compatible = "arm,scmi-shmem";
   reg = <0x0 0x100>;
  };
 };

 sata1: sata@fc400000 {
  compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
  reg = <0 0xfc400000 0 0x1000>;
  clocks = <&cru 155>, <&cru 156>,
    <&cru 157>;
  clock-names = "sata", "pmalive", "rxoob";
  interrupts = <0 95 4>;
  phys = <&combphy1 1>;
  phy-names = "sata-phy";
  ports-implemented = <0x1>;
  power-domains = <&power 15>;
  status = "disabled";
 };

 sata2: sata@fc800000 {
  compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
  reg = <0 0xfc800000 0 0x1000>;
  clocks = <&cru 160>, <&cru 161>,
    <&cru 162>;
  clock-names = "sata", "pmalive", "rxoob";
  interrupts = <0 96 4>;
  phys = <&combphy2 1>;
  phy-names = "sata-phy";
  ports-implemented = <0x1>;
  power-domains = <&power 15>;
  status = "disabled";
 };

 usb_host0_xhci: usb@fcc00000 {
  compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
  reg = <0x0 0xfcc00000 0x0 0x400000>;
  interrupts = <0 169 4>;
  clocks = <&cru 166>, <&cru 167>,
    <&cru 165>;
  clock-names = "ref_clk", "suspend_clk",
         "bus_clk";
  dr_mode = "otg";
  phy_type = "utmi_wide";
  power-domains = <&power 15>;
  resets = <&cru 148>;
  snps,dis_u2_susphy_quirk;
  status = "disabled";
 };

 usb_host1_xhci: usb@fd000000 {
  compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
  reg = <0x0 0xfd000000 0x0 0x400000>;
  interrupts = <0 170 4>;
  clocks = <&cru 169>, <&cru 170>,
    <&cru 168>;
  clock-names = "ref_clk", "suspend_clk",
         "bus_clk";
  dr_mode = "host";
  phys = <&usb2phy0_host>, <&combphy1 4>;
  phy-names = "usb2-phy", "usb3-phy";
  phy_type = "utmi_wide";
  power-domains = <&power 15>;
  resets = <&cru 149>;
  snps,dis_u2_susphy_quirk;
  status = "disabled";
 };

 gic: interrupt-controller@fd400000 {
  compatible = "arm,gic-v3";
  reg = <0x0 0xfd400000 0 0x10000>,
        <0x0 0xfd460000 0 0x80000>;
  interrupts = <1 9 4>;
  interrupt-controller;
  #interrupt-cells = <3>;
  mbi-alias = <0x0 0xfd410000>;
  mbi-ranges = <296 24>;
  msi-controller;
 };

 usb_host0_ehci: usb@fd800000 {
  compatible = "generic-ehci";
  reg = <0x0 0xfd800000 0x0 0x40000>;
  interrupts = <0 130 4>;
  clocks = <&cru 189>, <&cru 190>,
    <&cru 188>;
  phys = <&usb2phy1_otg>;
  phy-names = "usb";
  status = "disabled";
 };

 usb_host0_ohci: usb@fd840000 {
  compatible = "generic-ohci";
  reg = <0x0 0xfd840000 0x0 0x40000>;
  interrupts = <0 131 4>;
  clocks = <&cru 189>, <&cru 190>,
    <&cru 188>;
  phys = <&usb2phy1_otg>;
  phy-names = "usb";
  status = "disabled";
 };

 usb_host1_ehci: usb@fd880000 {
  compatible = "generic-ehci";
  reg = <0x0 0xfd880000 0x0 0x40000>;
  interrupts = <0 133 4>;
  clocks = <&cru 191>, <&cru 192>,
    <&cru 188>;
  phys = <&usb2phy1_host>;
  phy-names = "usb";
  status = "disabled";
 };

 usb_host1_ohci: usb@fd8c0000 {
  compatible = "generic-ohci";
  reg = <0x0 0xfd8c0000 0x0 0x40000>;
  interrupts = <0 134 4>;
  clocks = <&cru 191>, <&cru 192>,
    <&cru 188>;
  phys = <&usb2phy1_host>;
  phy-names = "usb";
  status = "disabled";
 };

 pmugrf: syscon@fdc20000 {
  compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
  reg = <0x0 0xfdc20000 0x0 0x10000>;

  pmu_io_domains: io-domains {
   compatible = "rockchip,rk3568-pmu-io-voltage-domain";
   status = "disabled";
  };
 };

 pipegrf: syscon@fdc50000 {
  reg = <0x0 0xfdc50000 0x0 0x1000>;
 };

 grf: syscon@fdc60000 {
  compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
  reg = <0x0 0xfdc60000 0x0 0x10000>;
 };

 pipe_phy_grf1: syscon@fdc80000 {
  compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
  reg = <0x0 0xfdc80000 0x0 0x1000>;
 };

 pipe_phy_grf2: syscon@fdc90000 {
  compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
  reg = <0x0 0xfdc90000 0x0 0x1000>;
 };

 usb2phy0_grf: syscon@fdca0000 {
  compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
  reg = <0x0 0xfdca0000 0x0 0x8000>;
 };

 usb2phy1_grf: syscon@fdca8000 {
  compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
  reg = <0x0 0xfdca8000 0x0 0x8000>;
 };

 pmucru: clock-controller@fdd00000 {
  compatible = "rockchip,rk3568-pmucru";
  reg = <0x0 0xfdd00000 0x0 0x1000>;
  #clock-cells = <1>;
  #reset-cells = <1>;
 };

 cru: clock-controller@fdd20000 {
  compatible = "rockchip,rk3568-cru";
  reg = <0x0 0xfdd20000 0x0 0x1000>;
  clocks = <&xin24m>;
  clock-names = "xin24m";
  #clock-cells = <1>;
  #reset-cells = <1>;
  assigned-clocks = <&pmucru 5>, <&cru 4>, <&pmucru 1>;
  assigned-clock-rates = <32768>, <1200000000>, <200000000>;
  assigned-clock-parents = <&pmucru 8>;
  rockchip,grf = <&grf>;
 };

 i2c0: i2c@fdd40000 {
  compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
  reg = <0x0 0xfdd40000 0x0 0x1000>;
  interrupts = <0 46 4>;
  clocks = <&pmucru 7>, <&pmucru 45>;
  clock-names = "i2c", "pclk";
  pinctrl-0 = <&i2c0_xfer>;
  pinctrl-names = "default";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 uart0: serial@fdd50000 {
  compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfdd50000 0x0 0x100>;
  interrupts = <0 116 4>;
  clocks = <&pmucru 11>, <&pmucru 44>;
  clock-names = "baudclk", "apb_pclk";
  dmas = <&dmac0 0>, <&dmac0 1>;
  pinctrl-0 = <&uart0_xfer>;
  pinctrl-names = "default";
  reg-io-width = <4>;
  reg-shift = <2>;
  status = "disabled";
 };

 pwm0: pwm@fdd70000 {
  compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfdd70000 0x0 0x10>;
  clocks = <&pmucru 13>, <&pmucru 48>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm0m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm1: pwm@fdd70010 {
  compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfdd70010 0x0 0x10>;
  clocks = <&pmucru 13>, <&pmucru 48>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm1m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm2: pwm@fdd70020 {
  compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfdd70020 0x0 0x10>;
  clocks = <&pmucru 13>, <&pmucru 48>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm2m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm3: pwm@fdd70030 {
  compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfdd70030 0x0 0x10>;
  clocks = <&pmucru 13>, <&pmucru 48>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm3_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pmu: power-management@fdd90000 {
  compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
  reg = <0x0 0xfdd90000 0x0 0x1000>;

  power: power-controller {
   compatible = "rockchip,rk3568-power-controller";
   #power-domain-cells = <1>;
   #address-cells = <1>;
   #size-cells = <0>;


   power-domain@7 {
    reg = <7>;
    clocks = <&cru 25>,
      <&cru 26>;
    pm_qos = <&qos_gpu>;
    #power-domain-cells = <0>;
   };


   power-domain@8 {
    reg = <8>;
    clocks = <&cru 204>,
      <&cru 205>;
    pm_qos = <&qos_isp>,
      <&qos_vicap0>,
      <&qos_vicap1>;
    #power-domain-cells = <0>;
   };

   power-domain@9 {
    reg = <9>;
    clocks = <&cru 218>,
      <&cru 219>,
      <&cru 220>;
    pm_qos = <&qos_hdcp>,
      <&qos_vop_m0>,
      <&qos_vop_m1>;
    #power-domain-cells = <0>;
   };

   power-domain@10 {
    reg = <10>;
    clocks = <&cru 241>,
      <&cru 242>;
    pm_qos = <&qos_ebc>,
      <&qos_iep>,
      <&qos_jpeg_dec>,
      <&qos_jpeg_enc>,
      <&qos_rga_rd>,
      <&qos_rga_wr>;
    #power-domain-cells = <0>;
   };

   power-domain@11 {
    reg = <11>;
    clocks = <&cru 237>;
    pm_qos = <&qos_vpu>;
    #power-domain-cells = <0>;
   };

   power-domain@13 {
    clocks = <&cru 263>;
    reg = <13>;
    pm_qos = <&qos_rkvdec>;
    #power-domain-cells = <0>;
   };

   power-domain@14 {
    reg = <14>;
    clocks = <&cru 258>;
    pm_qos = <&qos_rkvenc_rd_m0>,
      <&qos_rkvenc_rd_m1>,
      <&qos_rkvenc_wr_m0>;
    #power-domain-cells = <0>;
   };
  };
 };

 gpu: gpu@fde60000 {
  compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";
  reg = <0x0 0xfde60000 0x0 0x4000>;
  interrupts = <0 40 4>,
        <0 41 4>,
        <0 39 4>;
  interrupt-names = "job", "mmu", "gpu";
  clocks = <&scmi_clk 1>, <&cru 27>;
  clock-names = "gpu", "bus";
  #cooling-cells = <2>;
  operating-points-v2 = <&gpu_opp_table>;
  power-domains = <&power 7>;
  status = "disabled";
 };

 vpu: video-codec@fdea0400 {
  compatible = "rockchip,rk3568-vpu";
  reg = <0x0 0xfdea0000 0x0 0x800>;
  interrupts = <0 139 4>;
  clocks = <&cru 238>, <&cru 239>;
  clock-names = "aclk", "hclk";
  iommus = <&vdpu_mmu>;
  power-domains = <&power 11>;
 };

 vdpu_mmu: iommu@fdea0800 {
  compatible = "rockchip,rk3568-iommu";
  reg = <0x0 0xfdea0800 0x0 0x40>;
  interrupts = <0 138 4>;
  clock-names = "aclk", "iface";
  clocks = <&cru 238>, <&cru 239>;
  power-domains = <&power 11>;
  #iommu-cells = <0>;
 };

 rga: rga@fdeb0000 {
  compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga";
  reg = <0x0 0xfdeb0000 0x0 0x180>;
  interrupts = <0 90 4>;
  clocks = <&cru 243>, <&cru 244>, <&cru 245>;
  clock-names = "aclk", "hclk", "sclk";
  resets = <&cru 294>, <&cru 292>, <&cru 293>;
  reset-names = "core", "axi", "ahb";
  power-domains = <&power 10>;
 };

 vepu: video-codec@fdee0000 {
  compatible = "rockchip,rk3568-vepu";
  reg = <0x0 0xfdee0000 0x0 0x800>;
  interrupts = <0 64 4>;
  clocks = <&cru 253>, <&cru 254>;
  clock-names = "aclk", "hclk";
  iommus = <&vepu_mmu>;
  power-domains = <&power 10>;
 };

 vepu_mmu: iommu@fdee0800 {
  compatible = "rockchip,rk3568-iommu";
  reg = <0x0 0xfdee0800 0x0 0x40>;
  interrupts = <0 63 4>;
  clocks = <&cru 253>, <&cru 254>;
  clock-names = "aclk", "iface";
  power-domains = <&power 10>;
  #iommu-cells = <0>;
 };

 sdmmc2: mmc@fe000000 {
  compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
  reg = <0x0 0xfe000000 0x0 0x4000>;
  interrupts = <0 100 4>;
  clocks = <&cru 193>, <&cru 194>,
    <&cru 398>, <&cru 399>;
  clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  fifo-depth = <0x100>;
  max-frequency = <150000000>;
  resets = <&cru 235>;
  reset-names = "reset";
  status = "disabled";
 };

 gmac1: ethernet@fe010000 {
  compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
  reg = <0x0 0xfe010000 0x0 0x10000>;
  interrupts = <0 32 4>,
        <0 29 4>;
  interrupt-names = "macirq", "eth_wake_irq";
  clocks = <&cru 390>, <&cru 393>,
    <&cru 393>, <&cru 199>,
    <&cru 195>, <&cru 196>,
    <&cru 393>, <&cru 200>;
  clock-names = "stmmaceth", "mac_clk_rx",
         "mac_clk_tx", "clk_mac_refout",
         "aclk_mac", "pclk_mac",
         "clk_mac_speed", "ptp_ref";
  resets = <&cru 236>;
  reset-names = "stmmaceth";
  rockchip,grf = <&grf>;
  snps,axi-config = <&gmac1_stmmac_axi_setup>;
  snps,mixed-burst;
  snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
  snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
  snps,tso;
  status = "disabled";

  mdio1: mdio {
   compatible = "snps,dwmac-mdio";
   #address-cells = <0x1>;
   #size-cells = <0x0>;
  };

  gmac1_stmmac_axi_setup: stmmac-axi-config {
   snps,blen = <0 0 0 0 16 8 4>;
   snps,rd_osr_lmt = <8>;
   snps,wr_osr_lmt = <4>;
  };

  gmac1_mtl_rx_setup: rx-queues-config {
   snps,rx-queues-to-use = <1>;
   queue0 {};
  };

  gmac1_mtl_tx_setup: tx-queues-config {
   snps,tx-queues-to-use = <1>;
   queue0 {};
  };
 };

 vop: vop@fe040000 {
  reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
  reg-names = "vop", "gamma-lut";
  interrupts = <0 148 4>;
  clocks = <&cru 221>, <&cru 222>, <&cru 223>,
    <&cru 224>, <&cru 225>;
  clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2";
  iommus = <&vop_mmu>;
  power-domains = <&power 9>;
  rockchip,grf = <&grf>;
  status = "disabled";

  vop_out: ports {
   #address-cells = <1>;
   #size-cells = <0>;

   vp0: port@0 {
    reg = <0>;
    #address-cells = <1>;
    #size-cells = <0>;
   };

   vp1: port@1 {
    reg = <1>;
    #address-cells = <1>;
    #size-cells = <0>;
   };

   vp2: port@2 {
    reg = <2>;
    #address-cells = <1>;
    #size-cells = <0>;
   };
  };
 };

 vop_mmu: iommu@fe043e00 {
  compatible = "rockchip,rk3568-iommu";
  reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
  interrupts = <0 148 4>;
  clocks = <&cru 221>, <&cru 222>;
  clock-names = "aclk", "iface";
  #iommu-cells = <0>;
  status = "disabled";
 };

 dsi0: dsi@fe060000 {
  compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
  reg = <0x00 0xfe060000 0x00 0x10000>;
  interrupts = <0 68 4>;
  clock-names = "pclk";
  clocks = <&cru 232>;
  phy-names = "dphy";
  phys = <&dsi_dphy0>;
  power-domains = <&power 9>;
  reset-names = "apb";
  resets = <&cru 272>;
  rockchip,grf = <&grf>;
  status = "disabled";

  ports {
   #address-cells = <1>;
   #size-cells = <0>;

   dsi0_in: port@0 {
    reg = <0>;
   };

   dsi0_out: port@1 {
    reg = <1>;
   };
  };
 };

 dsi1: dsi@fe070000 {
  compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
  reg = <0x0 0xfe070000 0x0 0x10000>;
  interrupts = <0 69 4>;
  clock-names = "pclk";
  clocks = <&cru 233>;
  phy-names = "dphy";
  phys = <&dsi_dphy1>;
  power-domains = <&power 9>;
  reset-names = "apb";
  resets = <&cru 273>;
  rockchip,grf = <&grf>;
  status = "disabled";

  ports {
   #address-cells = <1>;
   #size-cells = <0>;

   dsi1_in: port@0 {
    reg = <0>;
   };

   dsi1_out: port@1 {
    reg = <1>;
   };
  };
 };

 hdmi: hdmi@fe0a0000 {
  compatible = "rockchip,rk3568-dw-hdmi";
  reg = <0x0 0xfe0a0000 0x0 0x20000>;
  interrupts = <0 45 4>;
  clocks = <&cru 230>,
    <&cru 231>,
    <&cru 403>,
    <&pmucru 40>,
    <&cru 218>;
  clock-names = "iahb", "isfr", "cec", "ref";
  pinctrl-names = "default";
  pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
  power-domains = <&power 9>;
  reg-io-width = <4>;
  rockchip,grf = <&grf>;
  #sound-dai-cells = <0>;
  status = "disabled";

  ports {
   #address-cells = <1>;
   #size-cells = <0>;

   hdmi_in: port@0 {
    reg = <0>;
   };

   hdmi_out: port@1 {
    reg = <1>;
   };
  };
 };

 qos_gpu: qos@fe128000 {
  compatible = "rockchip,rk3568-qos", "syscon";
  reg = <0x0 0xfe128000 0x0 0x20>;
 };

 qos_rkvenc_rd_m0: qos@fe138080 {
  compatible = "rockchip,rk3568-qos", "syscon";
  reg = <0x0 0xfe138080 0x0 0x20>;
 };

 qos_rkvenc_rd_m1: qos@fe138100 {
  compatible = "rockchip,rk3568-qos", "syscon";
  reg = <0x0 0xfe138100 0x0 0x20>;
 };

 qos_rkvenc_wr_m0: qos@fe138180 {
  compatible = "rockchip,rk3568-qos", "syscon";
  reg = <0x0 0xfe138180 0x0 0x20>;
 };

 qos_isp: qos@fe148000 {
  compatible = "rockchip,rk3568-qos", "syscon";
  reg = <0x0 0xfe148000 0x0 0x20>;
 };

 qos_vicap0: qos@fe148080 {
  compatible = "rockchip,rk3568-qos", "syscon";
  reg = <0x0 0xfe148080 0x0 0x20>;
 };

 qos_vicap1: qos@fe148100 {
  compatible = "rockchip,rk3568-qos", "syscon";
  reg = <0x0 0xfe148100 0x0 0x20>;
 };

 qos_vpu: qos@fe150000 {
  compatible = "rockchip,rk3568-qos", "syscon";
  reg = <0x0 0xfe150000 0x0 0x20>;
 };

 qos_ebc: qos@fe158000 {
  compatible = "rockchip,rk3568-qos", "syscon";
  reg = <0x0 0xfe158000 0x0 0x20>;
 };

 qos_iep: qos@fe158100 {
  compatible = "rockchip,rk3568-qos", "syscon";
  reg = <0x0 0xfe158100 0x0 0x20>;
 };

 qos_jpeg_dec: qos@fe158180 {
  compatible = "rockchip,rk3568-qos", "syscon";
  reg = <0x0 0xfe158180 0x0 0x20>;
 };

 qos_jpeg_enc: qos@fe158200 {
  compatible = "rockchip,rk3568-qos", "syscon";
  reg = <0x0 0xfe158200 0x0 0x20>;
 };

 qos_rga_rd: qos@fe158280 {
  compatible = "rockchip,rk3568-qos", "syscon";
  reg = <0x0 0xfe158280 0x0 0x20>;
 };

 qos_rga_wr: qos@fe158300 {
  compatible = "rockchip,rk3568-qos", "syscon";
  reg = <0x0 0xfe158300 0x0 0x20>;
 };

 qos_npu: qos@fe180000 {
  compatible = "rockchip,rk3568-qos", "syscon";
  reg = <0x0 0xfe180000 0x0 0x20>;
 };

 qos_pcie2x1: qos@fe190000 {
  compatible = "rockchip,rk3568-qos", "syscon";
  reg = <0x0 0xfe190000 0x0 0x20>;
 };

 qos_sata1: qos@fe190280 {
  compatible = "rockchip,rk3568-qos", "syscon";
  reg = <0x0 0xfe190280 0x0 0x20>;
 };

 qos_sata2: qos@fe190300 {
  compatible = "rockchip,rk3568-qos", "syscon";
  reg = <0x0 0xfe190300 0x0 0x20>;
 };

 qos_usb3_0: qos@fe190380 {
  compatible = "rockchip,rk3568-qos", "syscon";
  reg = <0x0 0xfe190380 0x0 0x20>;
 };

 qos_usb3_1: qos@fe190400 {
  compatible = "rockchip,rk3568-qos", "syscon";
  reg = <0x0 0xfe190400 0x0 0x20>;
 };

 qos_rkvdec: qos@fe198000 {
  compatible = "rockchip,rk3568-qos", "syscon";
  reg = <0x0 0xfe198000 0x0 0x20>;
 };

 qos_hdcp: qos@fe1a8000 {
  compatible = "rockchip,rk3568-qos", "syscon";
  reg = <0x0 0xfe1a8000 0x0 0x20>;
 };

 qos_vop_m0: qos@fe1a8080 {
  compatible = "rockchip,rk3568-qos", "syscon";
  reg = <0x0 0xfe1a8080 0x0 0x20>;
 };

 qos_vop_m1: qos@fe1a8100 {
  compatible = "rockchip,rk3568-qos", "syscon";
  reg = <0x0 0xfe1a8100 0x0 0x20>;
 };

 pcie2x1: pcie@fe260000 {
  compatible = "rockchip,rk3568-pcie";
  reg = <0x3 0xc0000000 0x0 0x00400000>,
        <0x0 0xfe260000 0x0 0x00010000>,
        <0x0 0xf4000000 0x0 0x00100000>;
  reg-names = "dbi", "apb", "config";
  interrupts = <0 75 4>,
        <0 74 4>,
        <0 73 4>,
        <0 72 4>,
        <0 71 4>;
  interrupt-names = "sys", "pmc", "msi", "legacy", "err";
  bus-range = <0x0 0xf>;
  clocks = <&cru 129>, <&cru 130>,
    <&cru 131>, <&cru 132>,
    <&cru 133>;
  clock-names = "aclk_mst", "aclk_slv",
         "aclk_dbi", "pclk", "aux";
  device_type = "pci";
  #interrupt-cells = <1>;
  interrupt-map-mask = <0 0 0 7>;
  interrupt-map = <0 0 0 1 &pcie_intc 0>,
    <0 0 0 2 &pcie_intc 1>,
    <0 0 0 3 &pcie_intc 2>,
    <0 0 0 4 &pcie_intc 3>;
  linux,pci-domain = <0>;
  num-ib-windows = <6>;
  num-ob-windows = <8>;
  max-link-speed = <2>;
  msi-map = <0x0 &gic 0x0 0x1000>;
  num-lanes = <1>;
  phys = <&combphy2 2>;
  phy-names = "pcie-phy";
  power-domains = <&power 15>;
  ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
    <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
    <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
  resets = <&cru 161>;
  reset-names = "pipe";
  #address-cells = <3>;
  #size-cells = <2>;
  status = "disabled";

  pcie_intc: legacy-interrupt-controller {
   #address-cells = <0>;
   #interrupt-cells = <1>;
   interrupt-controller;
   interrupt-parent = <&gic>;
   interrupts = <0 72 1>;
  };
 };

 sdmmc0: mmc@fe2b0000 {
  compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
  reg = <0x0 0xfe2b0000 0x0 0x4000>;
  interrupts = <0 98 4>;
  clocks = <&cru 176>, <&cru 177>,
    <&cru 394>, <&cru 395>;
  clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  fifo-depth = <0x100>;
  max-frequency = <150000000>;
  resets = <&cru 212>;
  reset-names = "reset";
  status = "disabled";
 };

 sdmmc1: mmc@fe2c0000 {
  compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
  reg = <0x0 0xfe2c0000 0x0 0x4000>;
  interrupts = <0 99 4>;
  clocks = <&cru 178>, <&cru 179>,
    <&cru 396>, <&cru 397>;
  clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  fifo-depth = <0x100>;
  max-frequency = <150000000>;
  resets = <&cru 214>;
  reset-names = "reset";
  status = "disabled";
 };

 sfc: spi@fe300000 {
  compatible = "rockchip,sfc";
  reg = <0x0 0xfe300000 0x0 0x4000>;
  interrupts = <0 101 4>;
  clocks = <&cru 120>, <&cru 118>;
  clock-names = "clk_sfc", "hclk_sfc";
  pinctrl-0 = <&fspi_pins>;
  pinctrl-names = "default";
  status = "disabled";
 };

 sdhci: mmc@fe310000 {
  compatible = "rockchip,rk3568-dwcmshc";
  reg = <0x0 0xfe310000 0x0 0x10000>;
  interrupts = <0 19 4>;
  assigned-clocks = <&cru 123>, <&cru 125>;
  assigned-clock-rates = <200000000>, <24000000>;
  clocks = <&cru 124>, <&cru 122>,
    <&cru 121>, <&cru 123>,
    <&cru 125>;
  clock-names = "core", "bus", "axi", "block", "timer";
  status = "disabled";
 };

 i2s0_8ch: i2s@fe400000 {
  compatible = "rockchip,rk3568-i2s-tdm";
  reg = <0x0 0xfe400000 0x0 0x1000>;
  interrupts = <0 52 4>;
  assigned-clocks = <&cru 61>, <&cru 65>;
  assigned-clock-rates = <1188000000>, <1188000000>;
  clocks = <&cru 63>, <&cru 67>, <&cru 57>;
  clock-names = "mclk_tx", "mclk_rx", "hclk";
  dmas = <&dmac1 0>;
  dma-names = "tx";
  resets = <&cru 80>, <&cru 81>;
  reset-names = "tx-m", "rx-m";
  rockchip,grf = <&grf>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 i2s1_8ch: i2s@fe410000 {
  compatible = "rockchip,rk3568-i2s-tdm";
  reg = <0x0 0xfe410000 0x0 0x1000>;
  interrupts = <0 53 4>;
  assigned-clocks = <&cru 69>, <&cru 73>;
  assigned-clock-rates = <1188000000>, <1188000000>;
  clocks = <&cru 71>, <&cru 75>,
    <&cru 58>;
  clock-names = "mclk_tx", "mclk_rx", "hclk";
  dmas = <&dmac1 3>, <&dmac1 2>;
  dma-names = "rx", "tx";
  resets = <&cru 82>, <&cru 83>;
  reset-names = "tx-m", "rx-m";
  rockchip,grf = <&grf>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
        &i2s1m0_lrcktx &i2s1m0_lrckrx
        &i2s1m0_sdi0 &i2s1m0_sdi1
        &i2s1m0_sdi2 &i2s1m0_sdi3
        &i2s1m0_sdo0 &i2s1m0_sdo1
        &i2s1m0_sdo2 &i2s1m0_sdo3>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 i2s2_2ch: i2s@fe420000 {
  compatible = "rockchip,rk3568-i2s-tdm";
  reg = <0x0 0xfe420000 0x0 0x1000>;
  interrupts = <0 54 4>;
  assigned-clocks = <&cru 77>;
  assigned-clock-rates = <1188000000>;
  clocks = <&cru 79>, <&cru 79>, <&cru 59>;
  clock-names = "mclk_tx", "mclk_rx", "hclk";
  dmas = <&dmac1 4>, <&dmac1 5>;
  dma-names = "tx", "rx";
  resets = <&cru 84>;
  reset-names = "m";
  rockchip,grf = <&grf>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2s2m0_sclktx
    &i2s2m0_lrcktx
    &i2s2m0_sdi
    &i2s2m0_sdo>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 i2s3_2ch: i2s@fe430000 {
  compatible = "rockchip,rk3568-i2s-tdm";
  reg = <0x0 0xfe430000 0x0 0x1000>;
  interrupts = <0 55 4>;
  clocks = <&cru 83>, <&cru 87>,
    <&cru 60>;
  clock-names = "mclk_tx", "mclk_rx", "hclk";
  dmas = <&dmac1 6>, <&dmac1 7>;
  dma-names = "tx", "rx";
  resets = <&cru 85>, <&cru 86>;
  reset-names = "tx-m", "rx-m";
  rockchip,grf = <&grf>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 pdm: pdm@fe440000 {
  compatible = "rockchip,rk3568-pdm";
  reg = <0x0 0xfe440000 0x0 0x1000>;
  interrupts = <0 76 4>;
  clocks = <&cru 90>, <&cru 89>;
  clock-names = "pdm_clk", "pdm_hclk";
  dmas = <&dmac1 9>;
  dma-names = "rx";
  pinctrl-0 = <&pdmm0_clk
        &pdmm0_clk1
        &pdmm0_sdi0
        &pdmm0_sdi1
        &pdmm0_sdi2
        &pdmm0_sdi3>;
  pinctrl-names = "default";
  resets = <&cru 88>;
  reset-names = "pdm-m";
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 spdif: spdif@fe460000 {
  compatible = "rockchip,rk3568-spdif";
  reg = <0x0 0xfe460000 0x0 0x1000>;
  interrupts = <0 102 4>;
  clock-names = "mclk", "hclk";
  clocks = <&cru 95>, <&cru 92>;
  dmas = <&dmac1 1>;
  dma-names = "tx";
  pinctrl-names = "default";
  pinctrl-0 = <&spdifm0_tx>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 dmac0: dma-controller@fe530000 {
  compatible = "arm,pl330", "arm,primecell";
  reg = <0x0 0xfe530000 0x0 0x4000>;
  interrupts = <0 14 4>,
        <0 13 4>;
  arm,pl330-periph-burst;
  clocks = <&cru 269>;
  clock-names = "apb_pclk";
  #dma-cells = <1>;
 };

 dmac1: dma-controller@fe550000 {
  compatible = "arm,pl330", "arm,primecell";
  reg = <0x0 0xfe550000 0x0 0x4000>;
  interrupts = <0 16 4>,
        <0 15 4>;
  arm,pl330-periph-burst;
  clocks = <&cru 269>;
  clock-names = "apb_pclk";
  #dma-cells = <1>;
 };

 i2c1: i2c@fe5a0000 {
  compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
  reg = <0x0 0xfe5a0000 0x0 0x1000>;
  interrupts = <0 47 4>;
  clocks = <&cru 328>, <&cru 327>;
  clock-names = "i2c", "pclk";
  pinctrl-0 = <&i2c1_xfer>;
  pinctrl-names = "default";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c2: i2c@fe5b0000 {
  compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
  reg = <0x0 0xfe5b0000 0x0 0x1000>;
  interrupts = <0 48 4>;
  clocks = <&cru 330>, <&cru 329>;
  clock-names = "i2c", "pclk";
  pinctrl-0 = <&i2c2m0_xfer>;
  pinctrl-names = "default";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c3: i2c@fe5c0000 {
  compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
  reg = <0x0 0xfe5c0000 0x0 0x1000>;
  interrupts = <0 49 4>;
  clocks = <&cru 332>, <&cru 331>;
  clock-names = "i2c", "pclk";
  pinctrl-0 = <&i2c3m0_xfer>;
  pinctrl-names = "default";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c4: i2c@fe5d0000 {
  compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
  reg = <0x0 0xfe5d0000 0x0 0x1000>;
  interrupts = <0 50 4>;
  clocks = <&cru 334>, <&cru 333>;
  clock-names = "i2c", "pclk";
  pinctrl-0 = <&i2c4m0_xfer>;
  pinctrl-names = "default";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c5: i2c@fe5e0000 {
  compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
  reg = <0x0 0xfe5e0000 0x0 0x1000>;
  interrupts = <0 51 4>;
  clocks = <&cru 336>, <&cru 335>;
  clock-names = "i2c", "pclk";
  pinctrl-0 = <&i2c5m0_xfer>;
  pinctrl-names = "default";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 wdt: watchdog@fe600000 {
  compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
  reg = <0x0 0xfe600000 0x0 0x100>;
  interrupts = <0 149 4>;
  clocks = <&cru 278>, <&cru 277>;
  clock-names = "tclk", "pclk";
 };

 spi0: spi@fe610000 {
  compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
  reg = <0x0 0xfe610000 0x0 0x1000>;
  interrupts = <0 103 4>;
  clocks = <&cru 338>, <&cru 337>;
  clock-names = "spiclk", "apb_pclk";
  dmas = <&dmac0 20>, <&dmac0 21>;
  dma-names = "tx", "rx";
  pinctrl-names = "default";
  pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 spi1: spi@fe620000 {
  compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
  reg = <0x0 0xfe620000 0x0 0x1000>;
  interrupts = <0 104 4>;
  clocks = <&cru 340>, <&cru 339>;
  clock-names = "spiclk", "apb_pclk";
  dmas = <&dmac0 22>, <&dmac0 23>;
  dma-names = "tx", "rx";
  pinctrl-names = "default";
  pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 spi2: spi@fe630000 {
  compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
  reg = <0x0 0xfe630000 0x0 0x1000>;
  interrupts = <0 105 4>;
  clocks = <&cru 342>, <&cru 341>;
  clock-names = "spiclk", "apb_pclk";
  dmas = <&dmac0 24>, <&dmac0 25>;
  dma-names = "tx", "rx";
  pinctrl-names = "default";
  pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 spi3: spi@fe640000 {
  compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
  reg = <0x0 0xfe640000 0x0 0x1000>;
  interrupts = <0 106 4>;
  clocks = <&cru 344>, <&cru 343>;
  clock-names = "spiclk", "apb_pclk";
  dmas = <&dmac0 26>, <&dmac0 27>;
  dma-names = "tx", "rx";
  pinctrl-names = "default";
  pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 uart1: serial@fe650000 {
  compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfe650000 0x0 0x100>;
  interrupts = <0 117 4>;
  clocks = <&cru 287>, <&cru 284>;
  clock-names = "baudclk", "apb_pclk";
  dmas = <&dmac0 2>, <&dmac0 3>;
  pinctrl-0 = <&uart1m0_xfer>;
  pinctrl-names = "default";
  reg-io-width = <4>;
  reg-shift = <2>;
  status = "disabled";
 };

 uart2: serial@fe660000 {
  compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfe660000 0x0 0x100>;
  interrupts = <0 118 4>;
  clocks = <&cru 291>, <&cru 288>;
  clock-names = "baudclk", "apb_pclk";
  dmas = <&dmac0 4>, <&dmac0 5>;
  pinctrl-0 = <&uart2m0_xfer>;
  pinctrl-names = "default";
  reg-io-width = <4>;
  reg-shift = <2>;
  status = "disabled";
 };

 uart3: serial@fe670000 {
  compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfe670000 0x0 0x100>;
  interrupts = <0 119 4>;
  clocks = <&cru 295>, <&cru 292>;
  clock-names = "baudclk", "apb_pclk";
  dmas = <&dmac0 6>, <&dmac0 7>;
  pinctrl-0 = <&uart3m0_xfer>;
  pinctrl-names = "default";
  reg-io-width = <4>;
  reg-shift = <2>;
  status = "disabled";
 };

 uart4: serial@fe680000 {
  compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfe680000 0x0 0x100>;
  interrupts = <0 120 4>;
  clocks = <&cru 299>, <&cru 296>;
  clock-names = "baudclk", "apb_pclk";
  dmas = <&dmac0 8>, <&dmac0 9>;
  pinctrl-0 = <&uart4m0_xfer>;
  pinctrl-names = "default";
  reg-io-width = <4>;
  reg-shift = <2>;
  status = "disabled";
 };

 uart5: serial@fe690000 {
  compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfe690000 0x0 0x100>;
  interrupts = <0 121 4>;
  clocks = <&cru 303>, <&cru 300>;
  clock-names = "baudclk", "apb_pclk";
  dmas = <&dmac0 10>, <&dmac0 11>;
  pinctrl-0 = <&uart5m0_xfer>;
  pinctrl-names = "default";
  reg-io-width = <4>;
  reg-shift = <2>;
  status = "disabled";
 };

 uart6: serial@fe6a0000 {
  compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfe6a0000 0x0 0x100>;
  interrupts = <0 122 4>;
  clocks = <&cru 307>, <&cru 304>;
  clock-names = "baudclk", "apb_pclk";
  dmas = <&dmac0 12>, <&dmac0 13>;
  pinctrl-0 = <&uart6m0_xfer>;
  pinctrl-names = "default";
  reg-io-width = <4>;
  reg-shift = <2>;
  status = "disabled";
 };

 uart7: serial@fe6b0000 {
  compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfe6b0000 0x0 0x100>;
  interrupts = <0 123 4>;
  clocks = <&cru 311>, <&cru 308>;
  clock-names = "baudclk", "apb_pclk";
  dmas = <&dmac0 14>, <&dmac0 15>;
  pinctrl-0 = <&uart7m0_xfer>;
  pinctrl-names = "default";
  reg-io-width = <4>;
  reg-shift = <2>;
  status = "disabled";
 };

 uart8: serial@fe6c0000 {
  compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfe6c0000 0x0 0x100>;
  interrupts = <0 124 4>;
  clocks = <&cru 315>, <&cru 312>;
  clock-names = "baudclk", "apb_pclk";
  dmas = <&dmac0 16>, <&dmac0 17>;
  pinctrl-0 = <&uart8m0_xfer>;
  pinctrl-names = "default";
  reg-io-width = <4>;
  reg-shift = <2>;
  status = "disabled";
 };

 uart9: serial@fe6d0000 {
  compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfe6d0000 0x0 0x100>;
  interrupts = <0 125 4>;
  clocks = <&cru 319>, <&cru 316>;
  clock-names = "baudclk", "apb_pclk";
  dmas = <&dmac0 18>, <&dmac0 19>;
  pinctrl-0 = <&uart9m0_xfer>;
  pinctrl-names = "default";
  reg-io-width = <4>;
  reg-shift = <2>;
  status = "disabled";
 };

 thermal_zones: thermal-zones {
  cpu_thermal: cpu-thermal {
   polling-delay-passive = <100>;
   polling-delay = <1000>;

   thermal-sensors = <&tsadc 0>;

   trips {
    cpu_alert0: cpu_alert0 {
     temperature = <70000>;
     hysteresis = <2000>;
     type = "passive";
    };
    cpu_alert1: cpu_alert1 {
     temperature = <75000>;
     hysteresis = <2000>;
     type = "passive";
    };
    cpu_crit: cpu_crit {
     temperature = <95000>;
     hysteresis = <2000>;
     type = "critical";
    };
   };

   cooling-maps {
    map0 {
     trip = <&cpu_alert0>;
     cooling-device =
      <&cpu0 (~0) (~0)>,
      <&cpu1 (~0) (~0)>,
      <&cpu2 (~0) (~0)>,
      <&cpu3 (~0) (~0)>;
    };
   };
  };

  gpu_thermal: gpu-thermal {
   polling-delay-passive = <20>;
   polling-delay = <1000>;

   thermal-sensors = <&tsadc 1>;

   trips {
    gpu_threshold: gpu-threshold {
     temperature = <70000>;
     hysteresis = <2000>;
     type = "passive";
    };
    gpu_target: gpu-target {
     temperature = <75000>;
     hysteresis = <2000>;
     type = "passive";
    };
    gpu_crit: gpu-crit {
     temperature = <95000>;
     hysteresis = <2000>;
     type = "critical";
    };
   };

   cooling-maps {
    map0 {
     trip = <&gpu_target>;
     cooling-device =
      <&gpu (~0) (~0)>;
    };
   };
  };
 };

 tsadc: tsadc@fe710000 {
  compatible = "rockchip,rk3568-tsadc";
  reg = <0x0 0xfe710000 0x0 0x100>;
  interrupts = <0 115 4>;
  assigned-clocks = <&cru 272>, <&cru 273>;
  assigned-clock-rates = <17000000>, <700000>;
  clocks = <&cru 273>, <&cru 271>;
  clock-names = "tsadc", "apb_pclk";
  resets = <&cru 385>, <&cru 386>,
    <&cru 471>;
  rockchip,grf = <&grf>;
  rockchip,hw-tshut-temp = <95000>;
  pinctrl-names = "init", "default", "sleep";
  pinctrl-0 = <&tsadc_pin>;
  pinctrl-1 = <&tsadc_shutorg>;
  pinctrl-2 = <&tsadc_pin>;
  #thermal-sensor-cells = <1>;
  status = "disabled";
 };

 saradc: saradc@fe720000 {
  compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
  reg = <0x0 0xfe720000 0x0 0x100>;
  interrupts = <0 93 4>;
  clocks = <&cru 275>, <&cru 274>;
  clock-names = "saradc", "apb_pclk";
  resets = <&cru 384>;
  reset-names = "saradc-apb";
  #io-channel-cells = <1>;
  status = "disabled";
 };

 pwm4: pwm@fe6e0000 {
  compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfe6e0000 0x0 0x10>;
  clocks = <&cru 346>, <&cru 345>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm4_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm5: pwm@fe6e0010 {
  compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfe6e0010 0x0 0x10>;
  clocks = <&cru 346>, <&cru 345>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm5_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm6: pwm@fe6e0020 {
  compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfe6e0020 0x0 0x10>;
  clocks = <&cru 346>, <&cru 345>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm6_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm7: pwm@fe6e0030 {
  compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfe6e0030 0x0 0x10>;
  clocks = <&cru 346>, <&cru 345>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm7_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm8: pwm@fe6f0000 {
  compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfe6f0000 0x0 0x10>;
  clocks = <&cru 349>, <&cru 348>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm8m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm9: pwm@fe6f0010 {
  compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfe6f0010 0x0 0x10>;
  clocks = <&cru 349>, <&cru 348>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm9m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm10: pwm@fe6f0020 {
  compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfe6f0020 0x0 0x10>;
  clocks = <&cru 349>, <&cru 348>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm10m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm11: pwm@fe6f0030 {
  compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfe6f0030 0x0 0x10>;
  clocks = <&cru 349>, <&cru 348>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm11m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm12: pwm@fe700000 {
  compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfe700000 0x0 0x10>;
  clocks = <&cru 352>, <&cru 351>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm12m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm13: pwm@fe700010 {
  compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfe700010 0x0 0x10>;
  clocks = <&cru 352>, <&cru 351>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm13m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm14: pwm@fe700020 {
  compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfe700020 0x0 0x10>;
  clocks = <&cru 352>, <&cru 351>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm14m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 pwm15: pwm@fe700030 {
  compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfe700030 0x0 0x10>;
  clocks = <&cru 352>, <&cru 351>;
  clock-names = "pwm", "pclk";
  pinctrl-0 = <&pwm15m0_pins>;
  pinctrl-names = "default";
  #pwm-cells = <3>;
  status = "disabled";
 };

 combphy1: phy@fe830000 {
  compatible = "rockchip,rk3568-naneng-combphy";
  reg = <0x0 0xfe830000 0x0 0x100>;
  clocks = <&pmucru 34>,
    <&cru 381>,
    <&cru 127>;
  clock-names = "ref", "apb", "pipe";
  assigned-clocks = <&pmucru 34>;
  assigned-clock-rates = <100000000>;
  resets = <&cru 455>;
  rockchip,pipe-grf = <&pipegrf>;
  rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
  #phy-cells = <1>;
  status = "disabled";
 };

 combphy2: phy@fe840000 {
  compatible = "rockchip,rk3568-naneng-combphy";
  reg = <0x0 0xfe840000 0x0 0x100>;
  clocks = <&pmucru 37>,
    <&cru 382>,
    <&cru 127>;
  clock-names = "ref", "apb", "pipe";
  assigned-clocks = <&pmucru 37>;
  assigned-clock-rates = <100000000>;
  resets = <&cru 457>;
  rockchip,pipe-grf = <&pipegrf>;
  rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
  #phy-cells = <1>;
  status = "disabled";
 };

 csi_dphy: phy@fe870000 {
  compatible = "rockchip,rk3568-csi-dphy";
  reg = <0x0 0xfe870000 0x0 0x10000>;
  clocks = <&cru 377>;
  clock-names = "pclk";
  #phy-cells = <0>;
  resets = <&cru 442>;
  reset-names = "apb";
  rockchip,grf = <&grf>;
  status = "disabled";
 };

 dsi_dphy0: mipi-dphy@fe850000 {
  compatible = "rockchip,rk3568-dsi-dphy";
  reg = <0x0 0xfe850000 0x0 0x10000>;
  clock-names = "ref", "pclk";
  clocks = <&pmucru 23>, <&cru 378>;
  #phy-cells = <0>;
  power-domains = <&power 9>;
  reset-names = "apb";
  resets = <&cru 443>;
  status = "disabled";
 };

 dsi_dphy1: mipi-dphy@fe860000 {
  compatible = "rockchip,rk3568-dsi-dphy";
  reg = <0x0 0xfe860000 0x0 0x10000>;
  clock-names = "ref", "pclk";
  clocks = <&pmucru 25>, <&cru 379>;
  #phy-cells = <0>;
  power-domains = <&power 9>;
  reset-names = "apb";
  resets = <&cru 444>;
  status = "disabled";
 };

 usb2phy0: usb2phy@fe8a0000 {
  compatible = "rockchip,rk3568-usb2phy";
  reg = <0x0 0xfe8a0000 0x0 0x10000>;
  clocks = <&pmucru 19>;
  clock-names = "phyclk";
  clock-output-names = "clk_usbphy0_480m";
  interrupts = <0 135 4>;
  rockchip,usbgrf = <&usb2phy0_grf>;
  #clock-cells = <0>;
  status = "disabled";

  usb2phy0_host: host-port {
   #phy-cells = <0>;
   status = "disabled";
  };

  usb2phy0_otg: otg-port {
   #phy-cells = <0>;
   status = "disabled";
  };
 };

 usb2phy1: usb2phy@fe8b0000 {
  compatible = "rockchip,rk3568-usb2phy";
  reg = <0x0 0xfe8b0000 0x0 0x10000>;
  clocks = <&pmucru 21>;
  clock-names = "phyclk";
  clock-output-names = "clk_usbphy1_480m";
  interrupts = <0 136 4>;
  rockchip,usbgrf = <&usb2phy1_grf>;
  #clock-cells = <0>;
  status = "disabled";

  usb2phy1_host: host-port {
   #phy-cells = <0>;
   status = "disabled";
  };

  usb2phy1_otg: otg-port {
   #phy-cells = <0>;
   status = "disabled";
  };
 };

 pinctrl: pinctrl {
  compatible = "rockchip,rk3568-pinctrl";
  rockchip,grf = <&grf>;
  rockchip,pmu = <&pmugrf>;
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;

  gpio0: gpio@fdd60000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xfdd60000 0x0 0x100>;
   interrupts = <0 33 4>;
   clocks = <&pmucru 46>, <&pmucru 12>;
   gpio-controller;
   gpio-ranges = <&pinctrl 0 0 32>;
   #gpio-cells = <2>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  gpio1: gpio@fe740000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xfe740000 0x0 0x100>;
   interrupts = <0 34 4>;
   clocks = <&cru 355>, <&cru 356>;
   gpio-controller;
   gpio-ranges = <&pinctrl 0 32 32>;
   #gpio-cells = <2>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  gpio2: gpio@fe750000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xfe750000 0x0 0x100>;
   interrupts = <0 35 4>;
   clocks = <&cru 357>, <&cru 358>;
   gpio-controller;
   gpio-ranges = <&pinctrl 0 64 32>;
   #gpio-cells = <2>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  gpio3: gpio@fe760000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xfe760000 0x0 0x100>;
   interrupts = <0 36 4>;
   clocks = <&cru 359>, <&cru 360>;
   gpio-controller;
   gpio-ranges = <&pinctrl 0 96 32>;
   #gpio-cells = <2>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  gpio4: gpio@fe770000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xfe770000 0x0 0x100>;
   interrupts = <0 37 4>;
   clocks = <&cru 361>, <&cru 362>;
   gpio-controller;
   gpio-ranges = <&pinctrl 0 128 32>;
   #gpio-cells = <2>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };
};

# 1 "arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi" 1






# 1 "arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi" 1





&pinctrl {
 /omit-if-no-ref/
 pcfg_pull_up: pcfg-pull-up {
  bias-pull-up;
 };

 /omit-if-no-ref/
 pcfg_pull_down: pcfg-pull-down {
  bias-pull-down;
 };

 /omit-if-no-ref/
 pcfg_pull_none: pcfg-pull-none {
  bias-disable;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
  bias-disable;
  drive-strength = <0>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
  bias-disable;
  drive-strength = <1>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
  bias-disable;
  drive-strength = <2>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
  bias-disable;
  drive-strength = <3>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 {
  bias-disable;
  drive-strength = <4>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 {
  bias-disable;
  drive-strength = <5>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 {
  bias-disable;
  drive-strength = <6>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 {
  bias-disable;
  drive-strength = <7>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 {
  bias-disable;
  drive-strength = <8>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 {
  bias-disable;
  drive-strength = <9>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 {
  bias-disable;
  drive-strength = <10>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 {
  bias-disable;
  drive-strength = <11>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 {
  bias-disable;
  drive-strength = <12>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 {
  bias-disable;
  drive-strength = <13>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 {
  bias-disable;
  drive-strength = <14>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 {
  bias-disable;
  drive-strength = <15>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 {
  bias-pull-up;
  drive-strength = <0>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 {
  bias-pull-up;
  drive-strength = <1>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 {
  bias-pull-up;
  drive-strength = <2>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 {
  bias-pull-up;
  drive-strength = <3>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 {
  bias-pull-up;
  drive-strength = <4>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 {
  bias-pull-up;
  drive-strength = <5>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 {
  bias-pull-up;
  drive-strength = <6>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 {
  bias-pull-up;
  drive-strength = <7>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 {
  bias-pull-up;
  drive-strength = <8>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 {
  bias-pull-up;
  drive-strength = <9>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 {
  bias-pull-up;
  drive-strength = <10>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 {
  bias-pull-up;
  drive-strength = <11>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 {
  bias-pull-up;
  drive-strength = <12>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 {
  bias-pull-up;
  drive-strength = <13>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 {
  bias-pull-up;
  drive-strength = <14>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 {
  bias-pull-up;
  drive-strength = <15>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 {
  bias-pull-down;
  drive-strength = <0>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 {
  bias-pull-down;
  drive-strength = <1>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 {
  bias-pull-down;
  drive-strength = <2>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 {
  bias-pull-down;
  drive-strength = <3>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 {
  bias-pull-down;
  drive-strength = <4>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 {
  bias-pull-down;
  drive-strength = <5>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 {
  bias-pull-down;
  drive-strength = <6>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 {
  bias-pull-down;
  drive-strength = <7>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 {
  bias-pull-down;
  drive-strength = <8>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 {
  bias-pull-down;
  drive-strength = <9>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 {
  bias-pull-down;
  drive-strength = <10>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 {
  bias-pull-down;
  drive-strength = <11>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 {
  bias-pull-down;
  drive-strength = <12>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 {
  bias-pull-down;
  drive-strength = <13>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 {
  bias-pull-down;
  drive-strength = <14>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 {
  bias-pull-down;
  drive-strength = <15>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_smt: pcfg-pull-up-smt {
  bias-pull-up;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_pull_down_smt: pcfg-pull-down-smt {
  bias-pull-down;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_pull_none_smt: pcfg-pull-none-smt {
  bias-disable;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt {
  bias-disable;
  drive-strength = <0>;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_output_high: pcfg-output-high {
  output-high;
 };

 /omit-if-no-ref/
 pcfg_output_low: pcfg-output-low {
  output-low;
 };
};
# 8 "arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi" 2





&pinctrl {
 acodec {
  /omit-if-no-ref/
  acodec_pins: acodec-pins {
   rockchip,pins =

    <1 9 5 &pcfg_pull_none>,

    <1 1 5 &pcfg_pull_none>,

    <1 0 5 &pcfg_pull_none>,

    <1 7 5 &pcfg_pull_none>,

    <1 8 5 &pcfg_pull_none>,

    <1 3 5 &pcfg_pull_none>,

    <1 5 5 &pcfg_pull_none>;
  };
 };

 audiopwm {
  /omit-if-no-ref/
  audiopwm_lout: audiopwm-lout {
   rockchip,pins =

    <1 0 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  audiopwm_loutn: audiopwm-loutn {
   rockchip,pins =

    <1 1 6 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  audiopwm_loutp: audiopwm-loutp {
   rockchip,pins =

    <1 0 6 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  audiopwm_rout: audiopwm-rout {
   rockchip,pins =

    <1 1 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  audiopwm_routn: audiopwm-routn {
   rockchip,pins =

    <1 7 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  audiopwm_routp: audiopwm-routp {
   rockchip,pins =

    <1 6 4 &pcfg_pull_none>;
  };
 };

 bt656 {
  /omit-if-no-ref/
  bt656m0_pins: bt656m0-pins {
   rockchip,pins =

    <3 0 2 &pcfg_pull_none>,

    <2 24 2 &pcfg_pull_none>,

    <2 25 2 &pcfg_pull_none>,

    <2 26 2 &pcfg_pull_none>,

    <2 27 2 &pcfg_pull_none>,

    <2 28 2 &pcfg_pull_none>,

    <2 29 2 &pcfg_pull_none>,

    <2 30 2 &pcfg_pull_none>,

    <2 31 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  bt656m1_pins: bt656m1-pins {
   rockchip,pins =

    <4 12 5 &pcfg_pull_none>,

    <3 22 5 &pcfg_pull_none>,

    <3 23 5 &pcfg_pull_none>,

    <3 24 5 &pcfg_pull_none>,

    <3 25 5 &pcfg_pull_none>,

    <3 26 5 &pcfg_pull_none>,

    <3 27 5 &pcfg_pull_none>,

    <3 28 5 &pcfg_pull_none>,

    <3 29 5 &pcfg_pull_none>;
  };
 };

 bt1120 {
  /omit-if-no-ref/
  bt1120_pins: bt1120-pins {
   rockchip,pins =

    <3 6 2 &pcfg_pull_none>,

    <3 1 2 &pcfg_pull_none>,

    <3 2 2 &pcfg_pull_none>,

    <3 3 2 &pcfg_pull_none>,

    <3 4 2 &pcfg_pull_none>,

    <3 5 2 &pcfg_pull_none>,

    <3 7 2 &pcfg_pull_none>,

    <3 8 2 &pcfg_pull_none>,

    <3 9 2 &pcfg_pull_none>,

    <3 10 2 &pcfg_pull_none>,

    <3 11 2 &pcfg_pull_none>,

    <3 12 2 &pcfg_pull_none>,

    <3 13 2 &pcfg_pull_none>,

    <3 14 2 &pcfg_pull_none>,

    <3 17 2 &pcfg_pull_none>,

    <3 18 2 &pcfg_pull_none>,

    <3 19 2 &pcfg_pull_none>;
  };
 };

 cam {
  /omit-if-no-ref/
  cam_clkout0: cam-clkout0 {
   rockchip,pins =

    <4 7 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  cam_clkout1: cam-clkout1 {
   rockchip,pins =

    <4 8 1 &pcfg_pull_none>;
  };
 };

 can0 {
  /omit-if-no-ref/
  can0m0_pins: can0m0-pins {
   rockchip,pins =

    <0 12 2 &pcfg_pull_none>,

    <0 11 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  can0m1_pins: can0m1-pins {
   rockchip,pins =

    <2 2 4 &pcfg_pull_none>,

    <2 1 4 &pcfg_pull_none>;
  };
 };

 can1 {
  /omit-if-no-ref/
  can1m0_pins: can1m0-pins {
   rockchip,pins =

    <1 0 3 &pcfg_pull_none>,

    <1 1 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  can1m1_pins: can1m1-pins {
   rockchip,pins =

    <4 18 3 &pcfg_pull_none>,

    <4 19 3 &pcfg_pull_none>;
  };
 };

 can2 {
  /omit-if-no-ref/
  can2m0_pins: can2m0-pins {
   rockchip,pins =

    <4 12 3 &pcfg_pull_none>,

    <4 13 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  can2m1_pins: can2m1-pins {
   rockchip,pins =

    <2 9 4 &pcfg_pull_none>,

    <2 10 4 &pcfg_pull_none>;
  };
 };

 cif {
  /omit-if-no-ref/
  cif_clk: cif-clk {
   rockchip,pins =

    <4 16 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  cif_dvp_clk: cif-dvp-clk {
   rockchip,pins =

    <4 17 1 &pcfg_pull_none>,

    <4 14 1 &pcfg_pull_none>,

    <4 15 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  cif_dvp_bus16: cif-dvp-bus16 {
   rockchip,pins =

    <3 30 1 &pcfg_pull_none>,

    <3 31 1 &pcfg_pull_none>,

    <4 0 1 &pcfg_pull_none>,

    <4 1 1 &pcfg_pull_none>,

    <4 2 1 &pcfg_pull_none>,

    <4 3 1 &pcfg_pull_none>,

    <4 4 1 &pcfg_pull_none>,

    <4 5 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  cif_dvp_bus8: cif-dvp-bus8 {
   rockchip,pins =

    <3 22 1 &pcfg_pull_none>,

    <3 23 1 &pcfg_pull_none>,

    <3 24 1 &pcfg_pull_none>,

    <3 25 1 &pcfg_pull_none>,

    <3 26 1 &pcfg_pull_none>,

    <3 27 1 &pcfg_pull_none>,

    <3 28 1 &pcfg_pull_none>,

    <3 29 1 &pcfg_pull_none>;
  };
 };

 clk32k {
  /omit-if-no-ref/
  clk32k_in: clk32k-in {
   rockchip,pins =

    <0 8 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  clk32k_out0: clk32k-out0 {
   rockchip,pins =

    <0 8 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  clk32k_out1: clk32k-out1 {
   rockchip,pins =

    <2 22 1 &pcfg_pull_none>;
  };
 };

 cpu {
  /omit-if-no-ref/
  cpu_pins: cpu-pins {
   rockchip,pins =

    <0 15 2 &pcfg_pull_none>;
  };
 };

 ebc {
  /omit-if-no-ref/
  ebc_extern: ebc-extern {
   rockchip,pins =

    <4 7 2 &pcfg_pull_none>,

    <4 8 2 &pcfg_pull_none>,

    <4 9 2 &pcfg_pull_none>,

    <4 13 2 &pcfg_pull_none>,

    <4 10 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  ebc_pins: ebc-pins {
   rockchip,pins =

    <4 16 2 &pcfg_pull_none>,

    <4 11 2 &pcfg_pull_none>,

    <4 12 2 &pcfg_pull_none>,

    <4 6 2 &pcfg_pull_none>,

    <4 17 2 &pcfg_pull_none>,

    <3 22 2 &pcfg_pull_none>,

    <3 23 2 &pcfg_pull_none>,

    <3 24 2 &pcfg_pull_none>,

    <3 25 2 &pcfg_pull_none>,

    <3 26 2 &pcfg_pull_none>,

    <3 27 2 &pcfg_pull_none>,

    <3 28 2 &pcfg_pull_none>,

    <3 29 2 &pcfg_pull_none>,

    <3 30 2 &pcfg_pull_none>,

    <3 31 2 &pcfg_pull_none>,

    <4 0 2 &pcfg_pull_none>,

    <4 1 2 &pcfg_pull_none>,

    <4 2 2 &pcfg_pull_none>,

    <4 3 2 &pcfg_pull_none>,

    <4 4 2 &pcfg_pull_none>,

    <4 5 2 &pcfg_pull_none>,

    <4 14 2 &pcfg_pull_none>,

    <4 15 2 &pcfg_pull_none>;
  };
 };

 edpdp {
  /omit-if-no-ref/
  edpdpm0_pins: edpdpm0-pins {
   rockchip,pins =

    <4 20 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  edpdpm1_pins: edpdpm1-pins {
   rockchip,pins =

    <0 18 2 &pcfg_pull_none>;
  };
 };

 emmc {
  /omit-if-no-ref/
  emmc_rstnout: emmc-rstnout {
   rockchip,pins =

    <1 23 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  emmc_bus8: emmc-bus8 {
   rockchip,pins =

    <1 12 1 &pcfg_pull_up_drv_level_2>,

    <1 13 1 &pcfg_pull_up_drv_level_2>,

    <1 14 1 &pcfg_pull_up_drv_level_2>,

    <1 15 1 &pcfg_pull_up_drv_level_2>,

    <1 16 1 &pcfg_pull_up_drv_level_2>,

    <1 17 1 &pcfg_pull_up_drv_level_2>,

    <1 18 1 &pcfg_pull_up_drv_level_2>,

    <1 19 1 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  emmc_clk: emmc-clk {
   rockchip,pins =

    <1 21 1 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  emmc_cmd: emmc-cmd {
   rockchip,pins =

    <1 20 1 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  emmc_datastrobe: emmc-datastrobe {
   rockchip,pins =

    <1 22 1 &pcfg_pull_none>;
  };
 };

 eth0 {
  /omit-if-no-ref/
  eth0_pins: eth0-pins {
   rockchip,pins =

    <2 17 2 &pcfg_pull_none>;
  };
 };

 eth1 {
  /omit-if-no-ref/
  eth1m0_pins: eth1m0-pins {
   rockchip,pins =

    <3 8 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  eth1m1_pins: eth1m1-pins {
   rockchip,pins =

    <4 11 3 &pcfg_pull_none>;
  };
 };

 flash {
  /omit-if-no-ref/
  flash_pins: flash-pins {
   rockchip,pins =

    <1 24 2 &pcfg_pull_none>,

    <1 22 3 &pcfg_pull_none>,

    <1 27 2 &pcfg_pull_none>,

    <1 28 2 &pcfg_pull_none>,

    <1 12 2 &pcfg_pull_none>,

    <1 13 2 &pcfg_pull_none>,

    <1 14 2 &pcfg_pull_none>,

    <1 15 2 &pcfg_pull_none>,

    <1 16 2 &pcfg_pull_none>,

    <1 17 2 &pcfg_pull_none>,

    <1 18 2 &pcfg_pull_none>,

    <1 19 2 &pcfg_pull_none>,

    <1 21 2 &pcfg_pull_none>,

    <1 26 2 &pcfg_pull_none>,

    <1 25 2 &pcfg_pull_none>,

    <0 7 1 &pcfg_pull_none>,

    <1 23 3 &pcfg_pull_none>,

    <1 20 2 &pcfg_pull_none>;
  };
 };

 fspi {
  /omit-if-no-ref/
  fspi_pins: fspi-pins {
   rockchip,pins =

    <1 24 1 &pcfg_pull_none>,

    <1 27 1 &pcfg_pull_none>,

    <1 25 1 &pcfg_pull_none>,

    <1 26 1 &pcfg_pull_none>,

    <1 23 2 &pcfg_pull_none>,

    <1 28 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  fspi_cs1: fspi-cs1 {
   rockchip,pins =

    <1 22 2 &pcfg_pull_up>;
  };
 };

 gmac0 {
  /omit-if-no-ref/
  gmac0_miim: gmac0-miim {
   rockchip,pins =

    <2 19 2 &pcfg_pull_none>,

    <2 20 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac0_clkinout: gmac0-clkinout {
   rockchip,pins =

    <2 18 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac0_rx_er: gmac0-rx-er {
   rockchip,pins =

    <2 21 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac0_rx_bus2: gmac0-rx-bus2 {
   rockchip,pins =

    <2 14 1 &pcfg_pull_none>,

    <2 15 2 &pcfg_pull_none>,

    <2 16 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac0_tx_bus2: gmac0-tx-bus2 {
   rockchip,pins =

    <2 11 1 &pcfg_pull_none_drv_level_2>,

    <2 12 1 &pcfg_pull_none_drv_level_2>,

    <2 13 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac0_rgmii_clk: gmac0-rgmii-clk {
   rockchip,pins =

    <2 5 2 &pcfg_pull_none>,

    <2 8 2 &pcfg_pull_none_drv_level_1>;
  };

  /omit-if-no-ref/
  gmac0_rgmii_bus: gmac0-rgmii-bus {
   rockchip,pins =

    <2 3 2 &pcfg_pull_none>,

    <2 4 2 &pcfg_pull_none>,

    <2 6 2 &pcfg_pull_none_drv_level_2>,

    <2 7 2 &pcfg_pull_none_drv_level_2>;
  };
 };

 gmac1 {
  /omit-if-no-ref/
  gmac1m0_miim: gmac1m0-miim {
   rockchip,pins =

    <3 20 3 &pcfg_pull_none>,

    <3 21 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1m0_clkinout: gmac1m0-clkinout {
   rockchip,pins =

    <3 16 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1m0_rx_er: gmac1m0-rx-er {
   rockchip,pins =

    <3 12 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1m0_rx_bus2: gmac1m0-rx-bus2 {
   rockchip,pins =

    <3 9 3 &pcfg_pull_none>,

    <3 10 3 &pcfg_pull_none>,

    <3 11 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1m0_tx_bus2: gmac1m0-tx-bus2 {
   rockchip,pins =

    <3 13 3 &pcfg_pull_none_drv_level_2>,

    <3 14 3 &pcfg_pull_none_drv_level_2>,

    <3 15 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1m0_rgmii_clk: gmac1m0-rgmii-clk {
   rockchip,pins =

    <3 7 3 &pcfg_pull_none>,

    <3 6 3 &pcfg_pull_none_drv_level_1>;
  };

  /omit-if-no-ref/
  gmac1m0_rgmii_bus: gmac1m0-rgmii-bus {
   rockchip,pins =

    <3 4 3 &pcfg_pull_none>,

    <3 5 3 &pcfg_pull_none>,

    <3 2 3 &pcfg_pull_none_drv_level_2>,

    <3 3 3 &pcfg_pull_none_drv_level_2>;
  };

  /omit-if-no-ref/
  gmac1m1_miim: gmac1m1-miim {
   rockchip,pins =

    <4 14 3 &pcfg_pull_none>,

    <4 15 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1m1_clkinout: gmac1m1-clkinout {
   rockchip,pins =

    <4 17 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1m1_rx_er: gmac1m1-rx-er {
   rockchip,pins =

    <4 10 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1m1_rx_bus2: gmac1m1-rx-bus2 {
   rockchip,pins =

    <4 7 3 &pcfg_pull_none>,

    <4 8 3 &pcfg_pull_none>,

    <4 9 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1m1_tx_bus2: gmac1m1-tx-bus2 {
   rockchip,pins =

    <4 4 3 &pcfg_pull_none_drv_level_2>,

    <4 5 3 &pcfg_pull_none_drv_level_2>,

    <4 6 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1m1_rgmii_clk: gmac1m1-rgmii-clk {
   rockchip,pins =

    <4 3 3 &pcfg_pull_none>,

    <4 0 3 &pcfg_pull_none_drv_level_1>;
  };

  /omit-if-no-ref/
  gmac1m1_rgmii_bus: gmac1m1-rgmii-bus {
   rockchip,pins =

    <4 1 3 &pcfg_pull_none>,

    <4 2 3 &pcfg_pull_none>,

    <3 30 3 &pcfg_pull_none_drv_level_2>,

    <3 31 3 &pcfg_pull_none_drv_level_2>;
  };
 };

 gpu {
  /omit-if-no-ref/
  gpu_pins: gpu-pins {
   rockchip,pins =

    <0 16 2 &pcfg_pull_none>,

    <0 6 4 &pcfg_pull_none>;
  };
 };

 hdmitx {
  /omit-if-no-ref/
  hdmitxm0_cec: hdmitxm0-cec {
   rockchip,pins =

    <4 25 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmitxm1_cec: hdmitxm1-cec {
   rockchip,pins =

    <0 23 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmitx_scl: hdmitx-scl {
   rockchip,pins =

    <4 23 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmitx_sda: hdmitx-sda {
   rockchip,pins =

    <4 24 1 &pcfg_pull_none>;
  };
 };

 i2c0 {
  /omit-if-no-ref/
  i2c0_xfer: i2c0-xfer {
   rockchip,pins =

    <0 9 1 &pcfg_pull_none_smt>,

    <0 10 1 &pcfg_pull_none_smt>;
  };
 };

 i2c1 {
  /omit-if-no-ref/
  i2c1_xfer: i2c1-xfer {
   rockchip,pins =

    <0 11 1 &pcfg_pull_none_smt>,

    <0 12 1 &pcfg_pull_none_smt>;
  };
 };

 i2c2 {
  /omit-if-no-ref/
  i2c2m0_xfer: i2c2m0-xfer {
   rockchip,pins =

    <0 13 1 &pcfg_pull_none_smt>,

    <0 14 1 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c2m1_xfer: i2c2m1-xfer {
   rockchip,pins =

    <4 13 1 &pcfg_pull_none_smt>,

    <4 12 1 &pcfg_pull_none_smt>;
  };
 };

 i2c3 {
  /omit-if-no-ref/
  i2c3m0_xfer: i2c3m0-xfer {
   rockchip,pins =

    <1 1 1 &pcfg_pull_none_smt>,

    <1 0 1 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c3m1_xfer: i2c3m1-xfer {
   rockchip,pins =

    <3 13 4 &pcfg_pull_none_smt>,

    <3 14 4 &pcfg_pull_none_smt>;
  };
 };

 i2c4 {
  /omit-if-no-ref/
  i2c4m0_xfer: i2c4m0-xfer {
   rockchip,pins =

    <4 11 1 &pcfg_pull_none_smt>,

    <4 10 1 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c4m1_xfer: i2c4m1-xfer {
   rockchip,pins =

    <2 10 2 &pcfg_pull_none_smt>,

    <2 9 2 &pcfg_pull_none_smt>;
  };
 };

 i2c5 {
  /omit-if-no-ref/
  i2c5m0_xfer: i2c5m0-xfer {
   rockchip,pins =

    <3 11 4 &pcfg_pull_none_smt>,

    <3 12 4 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c5m1_xfer: i2c5m1-xfer {
   rockchip,pins =

    <4 23 2 &pcfg_pull_none_smt>,

    <4 24 2 &pcfg_pull_none_smt>;
  };
 };

 i2s1 {
  /omit-if-no-ref/
  i2s1m0_lrckrx: i2s1m0-lrckrx {
   rockchip,pins =

    <1 6 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_lrcktx: i2s1m0-lrcktx {
   rockchip,pins =

    <1 5 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_mclk: i2s1m0-mclk {
   rockchip,pins =

    <1 2 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_sclkrx: i2s1m0-sclkrx {
   rockchip,pins =

    <1 4 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_sclktx: i2s1m0-sclktx {
   rockchip,pins =

    <1 3 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_sdi0: i2s1m0-sdi0 {
   rockchip,pins =

    <1 11 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_sdi1: i2s1m0-sdi1 {
   rockchip,pins =

    <1 10 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_sdi2: i2s1m0-sdi2 {
   rockchip,pins =

    <1 9 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_sdi3: i2s1m0-sdi3 {
   rockchip,pins =

    <1 8 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_sdo0: i2s1m0-sdo0 {
   rockchip,pins =

    <1 7 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_sdo1: i2s1m0-sdo1 {
   rockchip,pins =

    <1 8 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_sdo2: i2s1m0-sdo2 {
   rockchip,pins =

    <1 9 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_sdo3: i2s1m0-sdo3 {
   rockchip,pins =

    <1 10 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_lrckrx: i2s1m1-lrckrx {
   rockchip,pins =

    <4 7 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_lrcktx: i2s1m1-lrcktx {
   rockchip,pins =

    <3 24 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_mclk: i2s1m1-mclk {
   rockchip,pins =

    <3 22 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_sclkrx: i2s1m1-sclkrx {
   rockchip,pins =

    <4 6 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_sclktx: i2s1m1-sclktx {
   rockchip,pins =

    <3 23 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_sdi0: i2s1m1-sdi0 {
   rockchip,pins =

    <3 26 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_sdi1: i2s1m1-sdi1 {
   rockchip,pins =

    <3 27 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_sdi2: i2s1m1-sdi2 {
   rockchip,pins =

    <3 28 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_sdi3: i2s1m1-sdi3 {
   rockchip,pins =

    <3 29 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_sdo0: i2s1m1-sdo0 {
   rockchip,pins =

    <3 25 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_sdo1: i2s1m1-sdo1 {
   rockchip,pins =

    <4 8 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_sdo2: i2s1m1-sdo2 {
   rockchip,pins =

    <4 9 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_sdo3: i2s1m1-sdo3 {
   rockchip,pins =

    <4 13 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m2_lrckrx: i2s1m2-lrckrx {
   rockchip,pins =

    <3 21 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m2_lrcktx: i2s1m2-lrcktx {
   rockchip,pins =

    <2 26 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m2_mclk: i2s1m2-mclk {
   rockchip,pins =

    <2 24 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m2_sclkrx: i2s1m2-sclkrx {
   rockchip,pins =

    <3 19 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m2_sclktx: i2s1m2-sclktx {
   rockchip,pins =

    <2 25 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m2_sdi0: i2s1m2-sdi0 {
   rockchip,pins =

    <2 27 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m2_sdi1: i2s1m2-sdi1 {
   rockchip,pins =

    <2 28 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m2_sdi2: i2s1m2-sdi2 {
   rockchip,pins =

    <2 29 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m2_sdi3: i2s1m2-sdi3 {
   rockchip,pins =

    <2 30 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m2_sdo0: i2s1m2-sdo0 {
   rockchip,pins =

    <2 31 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m2_sdo1: i2s1m2-sdo1 {
   rockchip,pins =

    <3 0 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m2_sdo2: i2s1m2-sdo2 {
   rockchip,pins =

    <3 17 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m2_sdo3: i2s1m2-sdo3 {
   rockchip,pins =

    <3 18 5 &pcfg_pull_none>;
  };
 };

 i2s2 {
  /omit-if-no-ref/
  i2s2m0_lrckrx: i2s2m0-lrckrx {
   rockchip,pins =

    <2 16 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m0_lrcktx: i2s2m0-lrcktx {
   rockchip,pins =

    <2 19 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m0_mclk: i2s2m0-mclk {
   rockchip,pins =

    <2 17 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m0_sclkrx: i2s2m0-sclkrx {
   rockchip,pins =

    <2 15 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m0_sclktx: i2s2m0-sclktx {
   rockchip,pins =

    <2 18 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m0_sdi: i2s2m0-sdi {
   rockchip,pins =

    <2 21 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m0_sdo: i2s2m0-sdo {
   rockchip,pins =

    <2 20 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m1_lrckrx: i2s2m1-lrckrx {
   rockchip,pins =

    <4 5 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m1_lrcktx: i2s2m1-lrcktx {
   rockchip,pins =

    <4 4 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m1_mclk: i2s2m1-mclk {
   rockchip,pins =

    <4 14 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m1_sclkrx: i2s2m1-sclkrx {
   rockchip,pins =

    <4 17 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m1_sclktx: i2s2m1-sclktx {
   rockchip,pins =

    <4 15 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m1_sdi: i2s2m1-sdi {
   rockchip,pins =

    <4 10 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m1_sdo: i2s2m1-sdo {
   rockchip,pins =

    <4 11 5 &pcfg_pull_none>;
  };
 };

 i2s3 {
  /omit-if-no-ref/
  i2s3m0_lrck: i2s3m0-lrck {
   rockchip,pins =

    <3 4 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s3m0_mclk: i2s3m0-mclk {
   rockchip,pins =

    <3 2 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s3m0_sclk: i2s3m0-sclk {
   rockchip,pins =

    <3 3 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s3m0_sdi: i2s3m0-sdi {
   rockchip,pins =

    <3 6 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s3m0_sdo: i2s3m0-sdo {
   rockchip,pins =

    <3 5 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s3m1_lrck: i2s3m1-lrck {
   rockchip,pins =

    <4 20 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s3m1_mclk: i2s3m1-mclk {
   rockchip,pins =

    <4 18 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s3m1_sclk: i2s3m1-sclk {
   rockchip,pins =

    <4 19 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s3m1_sdi: i2s3m1-sdi {
   rockchip,pins =

    <4 22 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s3m1_sdo: i2s3m1-sdo {
   rockchip,pins =

    <4 21 5 &pcfg_pull_none>;
  };
 };

 isp {
  /omit-if-no-ref/
  isp_pins: isp-pins {
   rockchip,pins =

    <4 12 4 &pcfg_pull_none>,

    <4 6 1 &pcfg_pull_none>,

    <4 9 1 &pcfg_pull_none>;
  };
 };

 jtag {
  /omit-if-no-ref/
  jtag_pins: jtag-pins {
   rockchip,pins =

    <1 31 2 &pcfg_pull_none>,

    <2 0 2 &pcfg_pull_none>;
  };
 };

 lcdc {
  /omit-if-no-ref/
  lcdc_ctl: lcdc-ctl {
   rockchip,pins =

    <3 0 1 &pcfg_pull_none>,

    <2 24 1 &pcfg_pull_none>,

    <2 25 1 &pcfg_pull_none>,

    <2 26 1 &pcfg_pull_none>,

    <2 27 1 &pcfg_pull_none>,

    <2 28 1 &pcfg_pull_none>,

    <2 29 1 &pcfg_pull_none>,

    <2 30 1 &pcfg_pull_none>,

    <2 31 1 &pcfg_pull_none>,

    <3 1 1 &pcfg_pull_none>,

    <3 2 1 &pcfg_pull_none>,

    <3 3 1 &pcfg_pull_none>,

    <3 4 1 &pcfg_pull_none>,

    <3 5 1 &pcfg_pull_none>,

    <3 6 1 &pcfg_pull_none>,

    <3 7 1 &pcfg_pull_none>,

    <3 8 1 &pcfg_pull_none>,

    <3 9 1 &pcfg_pull_none>,

    <3 10 1 &pcfg_pull_none>,

    <3 11 1 &pcfg_pull_none>,

    <3 12 1 &pcfg_pull_none>,

    <3 13 1 &pcfg_pull_none>,

    <3 14 1 &pcfg_pull_none>,

    <3 15 1 &pcfg_pull_none>,

    <3 16 1 &pcfg_pull_none>,

    <3 19 1 &pcfg_pull_none>,

    <3 17 1 &pcfg_pull_none>,

    <3 18 1 &pcfg_pull_none>;
  };
 };

 mcu {
  /omit-if-no-ref/
  mcu_pins: mcu-pins {
   rockchip,pins =

    <0 12 4 &pcfg_pull_none>,

    <0 17 4 &pcfg_pull_none>,

    <0 11 4 &pcfg_pull_none>,

    <0 18 4 &pcfg_pull_none>,

    <0 19 4 &pcfg_pull_none>;
  };
 };

 npu {
  /omit-if-no-ref/
  npu_pins: npu-pins {
   rockchip,pins =

    <0 17 2 &pcfg_pull_none>;
  };
 };

 pcie20 {
  /omit-if-no-ref/
  pcie20m0_pins: pcie20m0-pins {
   rockchip,pins =

    <0 5 3 &pcfg_pull_none>,

    <0 14 3 &pcfg_pull_none>,

    <0 13 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie20m1_pins: pcie20m1-pins {
   rockchip,pins =

    <2 24 4 &pcfg_pull_none>,

    <3 17 4 &pcfg_pull_none>,

    <2 25 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie20m2_pins: pcie20m2-pins {
   rockchip,pins =

    <1 8 4 &pcfg_pull_none>,

    <1 10 4 &pcfg_pull_none>,

    <1 9 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie20_buttonrstn: pcie20-buttonrstn {
   rockchip,pins =

    <0 12 3 &pcfg_pull_none>;
  };
 };

 pcie30x1 {
  /omit-if-no-ref/
  pcie30x1m0_pins: pcie30x1m0-pins {
   rockchip,pins =

    <0 4 3 &pcfg_pull_none>,

    <0 19 3 &pcfg_pull_none>,

    <0 18 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x1m1_pins: pcie30x1m1-pins {
   rockchip,pins =

    <2 26 4 &pcfg_pull_none>,

    <3 1 4 &pcfg_pull_none>,

    <2 27 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x1m2_pins: pcie30x1m2-pins {
   rockchip,pins =

    <1 5 4 &pcfg_pull_none>,

    <1 2 4 &pcfg_pull_none>,

    <1 3 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x1_buttonrstn: pcie30x1-buttonrstn {
   rockchip,pins =

    <0 11 3 &pcfg_pull_none>;
  };
 };

 pcie30x2 {
  /omit-if-no-ref/
  pcie30x2m0_pins: pcie30x2m0-pins {
   rockchip,pins =

    <0 6 2 &pcfg_pull_none>,

    <0 22 3 &pcfg_pull_none>,

    <0 21 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x2m1_pins: pcie30x2m1-pins {
   rockchip,pins =

    <2 28 4 &pcfg_pull_none>,

    <2 30 4 &pcfg_pull_none>,

    <2 29 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x2m2_pins: pcie30x2m2-pins {
   rockchip,pins =

    <4 18 4 &pcfg_pull_none>,

    <4 20 4 &pcfg_pull_none>,

    <4 19 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x2_buttonrstn: pcie30x2-buttonrstn {
   rockchip,pins =

    <0 8 3 &pcfg_pull_none>;
  };
 };

 pdm {
  /omit-if-no-ref/
  pdmm0_clk: pdmm0-clk {
   rockchip,pins =

    <1 6 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdmm0_clk1: pdmm0-clk1 {
   rockchip,pins =

    <1 4 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdmm0_sdi0: pdmm0-sdi0 {
   rockchip,pins =

    <1 11 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdmm0_sdi1: pdmm0-sdi1 {
   rockchip,pins =

    <1 10 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdmm0_sdi2: pdmm0-sdi2 {
   rockchip,pins =

    <1 9 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdmm0_sdi3: pdmm0-sdi3 {
   rockchip,pins =

    <1 8 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdmm1_clk: pdmm1-clk {
   rockchip,pins =

    <3 30 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdmm1_clk1: pdmm1-clk1 {
   rockchip,pins =

    <4 0 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdmm1_sdi0: pdmm1-sdi0 {
   rockchip,pins =

    <3 31 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdmm1_sdi1: pdmm1-sdi1 {
   rockchip,pins =

    <4 1 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdmm1_sdi2: pdmm1-sdi2 {
   rockchip,pins =

    <4 2 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdmm1_sdi3: pdmm1-sdi3 {
   rockchip,pins =

    <4 3 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdmm2_clk1: pdmm2-clk1 {
   rockchip,pins =

    <3 20 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdmm2_sdi0: pdmm2-sdi0 {
   rockchip,pins =

    <3 11 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdmm2_sdi1: pdmm2-sdi1 {
   rockchip,pins =

    <3 12 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdmm2_sdi2: pdmm2-sdi2 {
   rockchip,pins =

    <3 15 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdmm2_sdi3: pdmm2-sdi3 {
   rockchip,pins =

    <3 16 5 &pcfg_pull_none>;
  };
 };

 pmic {
  /omit-if-no-ref/
  pmic_pins: pmic-pins {
   rockchip,pins =

    <0 2 1 &pcfg_pull_none>;
  };
 };

 pmu {
  /omit-if-no-ref/
  pmu_pins: pmu-pins {
   rockchip,pins =

    <0 5 4 &pcfg_pull_none>,

    <0 6 3 &pcfg_pull_none>,

    <0 20 4 &pcfg_pull_none>,

    <0 21 4 &pcfg_pull_none>,

    <0 22 4 &pcfg_pull_none>,

    <0 23 4 &pcfg_pull_none>;
  };
 };

 pwm0 {
  /omit-if-no-ref/
  pwm0m0_pins: pwm0m0-pins {
   rockchip,pins =

    <0 15 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm0m1_pins: pwm0m1-pins {
   rockchip,pins =

    <0 23 2 &pcfg_pull_none>;
  };
 };

 pwm1 {
  /omit-if-no-ref/
  pwm1m0_pins: pwm1m0-pins {
   rockchip,pins =

    <0 16 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm1m1_pins: pwm1m1-pins {
   rockchip,pins =

    <0 13 4 &pcfg_pull_none>;
  };
 };

 pwm2 {
  /omit-if-no-ref/
  pwm2m0_pins: pwm2m0-pins {
   rockchip,pins =

    <0 17 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm2m1_pins: pwm2m1-pins {
   rockchip,pins =

    <0 14 4 &pcfg_pull_none>;
  };
 };

 pwm3 {
  /omit-if-no-ref/
  pwm3_pins: pwm3-pins {
   rockchip,pins =

    <0 18 1 &pcfg_pull_none>;
  };
 };

 pwm4 {
  /omit-if-no-ref/
  pwm4_pins: pwm4-pins {
   rockchip,pins =

    <0 19 1 &pcfg_pull_none>;
  };
 };

 pwm5 {
  /omit-if-no-ref/
  pwm5_pins: pwm5-pins {
   rockchip,pins =

    <0 20 1 &pcfg_pull_none>;
  };
 };

 pwm6 {
  /omit-if-no-ref/
  pwm6_pins: pwm6-pins {
   rockchip,pins =

    <0 21 1 &pcfg_pull_none>;
  };
 };

 pwm7 {
  /omit-if-no-ref/
  pwm7_pins: pwm7-pins {
   rockchip,pins =

    <0 22 1 &pcfg_pull_none>;
  };
 };

 pwm8 {
  /omit-if-no-ref/
  pwm8m0_pins: pwm8m0-pins {
   rockchip,pins =

    <3 9 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm8m1_pins: pwm8m1-pins {
   rockchip,pins =

    <1 29 4 &pcfg_pull_none>;
  };
 };

 pwm9 {
  /omit-if-no-ref/
  pwm9m0_pins: pwm9m0-pins {
   rockchip,pins =

    <3 10 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm9m1_pins: pwm9m1-pins {
   rockchip,pins =

    <1 30 4 &pcfg_pull_none>;
  };
 };

 pwm10 {
  /omit-if-no-ref/
  pwm10m0_pins: pwm10m0-pins {
   rockchip,pins =

    <3 13 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm10m1_pins: pwm10m1-pins {
   rockchip,pins =

    <2 1 2 &pcfg_pull_none>;
  };
 };

 pwm11 {
  /omit-if-no-ref/
  pwm11m0_pins: pwm11m0-pins {
   rockchip,pins =

    <3 14 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm11m1_pins: pwm11m1-pins {
   rockchip,pins =

    <4 16 3 &pcfg_pull_none>;
  };
 };

 pwm12 {
  /omit-if-no-ref/
  pwm12m0_pins: pwm12m0-pins {
   rockchip,pins =

    <3 15 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm12m1_pins: pwm12m1-pins {
   rockchip,pins =

    <4 21 1 &pcfg_pull_none>;
  };
 };

 pwm13 {
  /omit-if-no-ref/
  pwm13m0_pins: pwm13m0-pins {
   rockchip,pins =

    <3 16 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm13m1_pins: pwm13m1-pins {
   rockchip,pins =

    <4 22 1 &pcfg_pull_none>;
  };
 };

 pwm14 {
  /omit-if-no-ref/
  pwm14m0_pins: pwm14m0-pins {
   rockchip,pins =

    <3 20 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm14m1_pins: pwm14m1-pins {
   rockchip,pins =

    <4 18 1 &pcfg_pull_none>;
  };
 };

 pwm15 {
  /omit-if-no-ref/
  pwm15m0_pins: pwm15m0-pins {
   rockchip,pins =

    <3 21 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm15m1_pins: pwm15m1-pins {
   rockchip,pins =

    <4 19 1 &pcfg_pull_none>;
  };
 };

 refclk {
  /omit-if-no-ref/
  refclk_pins: refclk-pins {
   rockchip,pins =

    <0 0 1 &pcfg_pull_none>;
  };
 };

 sata {
  /omit-if-no-ref/
  sata_pins: sata-pins {
   rockchip,pins =

    <0 4 2 &pcfg_pull_none>,

    <0 6 1 &pcfg_pull_none>,

    <0 5 2 &pcfg_pull_none>;
  };
 };

 sata0 {
  /omit-if-no-ref/
  sata0_pins: sata0-pins {
   rockchip,pins =

    <4 22 3 &pcfg_pull_none>;
  };
 };

 sata1 {
  /omit-if-no-ref/
  sata1_pins: sata1-pins {
   rockchip,pins =

    <4 21 3 &pcfg_pull_none>;
  };
 };

 sata2 {
  /omit-if-no-ref/
  sata2_pins: sata2-pins {
   rockchip,pins =

    <4 20 3 &pcfg_pull_none>;
  };
 };

 scr {
  /omit-if-no-ref/
  scr_pins: scr-pins {
   rockchip,pins =

    <1 2 3 &pcfg_pull_none>,

    <1 7 3 &pcfg_pull_up>,

    <1 3 3 &pcfg_pull_up>,

    <1 5 3 &pcfg_pull_none>;
  };
 };

 sdmmc0 {
  /omit-if-no-ref/
  sdmmc0_bus4: sdmmc0-bus4 {
   rockchip,pins =

    <1 29 1 &pcfg_pull_up_drv_level_2>,

    <1 30 1 &pcfg_pull_up_drv_level_2>,

    <1 31 1 &pcfg_pull_up_drv_level_2>,

    <2 0 1 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  sdmmc0_clk: sdmmc0-clk {
   rockchip,pins =

    <2 2 1 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  sdmmc0_cmd: sdmmc0-cmd {
   rockchip,pins =

    <2 1 1 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  sdmmc0_det: sdmmc0-det {
   rockchip,pins =

    <0 4 1 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  sdmmc0_pwren: sdmmc0-pwren {
   rockchip,pins =

    <0 5 1 &pcfg_pull_none>;
  };
 };

 sdmmc1 {
  /omit-if-no-ref/
  sdmmc1_bus4: sdmmc1-bus4 {
   rockchip,pins =

    <2 3 1 &pcfg_pull_up_drv_level_2>,

    <2 4 1 &pcfg_pull_up_drv_level_2>,

    <2 5 1 &pcfg_pull_up_drv_level_2>,

    <2 6 1 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  sdmmc1_clk: sdmmc1-clk {
   rockchip,pins =

    <2 8 1 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  sdmmc1_cmd: sdmmc1-cmd {
   rockchip,pins =

    <2 7 1 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  sdmmc1_det: sdmmc1-det {
   rockchip,pins =

    <2 10 1 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  sdmmc1_pwren: sdmmc1-pwren {
   rockchip,pins =

    <2 9 1 &pcfg_pull_none>;
  };
 };

 sdmmc2 {
  /omit-if-no-ref/
  sdmmc2m0_bus4: sdmmc2m0-bus4 {
   rockchip,pins =

    <3 22 3 &pcfg_pull_up_drv_level_2>,

    <3 23 3 &pcfg_pull_up_drv_level_2>,

    <3 24 3 &pcfg_pull_up_drv_level_2>,

    <3 25 3 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  sdmmc2m0_clk: sdmmc2m0-clk {
   rockchip,pins =

    <3 27 3 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  sdmmc2m0_cmd: sdmmc2m0-cmd {
   rockchip,pins =

    <3 26 3 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  sdmmc2m0_det: sdmmc2m0-det {
   rockchip,pins =

    <3 28 3 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  sdmmc2m0_pwren: sdmmc2m0-pwren {
   rockchip,pins =

    <3 29 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  sdmmc2m1_bus4: sdmmc2m1-bus4 {
   rockchip,pins =

    <3 1 5 &pcfg_pull_up_drv_level_2>,

    <3 2 5 &pcfg_pull_up_drv_level_2>,

    <3 3 5 &pcfg_pull_up_drv_level_2>,

    <3 4 5 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  sdmmc2m1_clk: sdmmc2m1-clk {
   rockchip,pins =

    <3 6 5 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  sdmmc2m1_cmd: sdmmc2m1-cmd {
   rockchip,pins =

    <3 5 5 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  sdmmc2m1_det: sdmmc2m1-det {
   rockchip,pins =

    <3 7 4 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  sdmmc2m1_pwren: sdmmc2m1-pwren {
   rockchip,pins =

    <3 8 4 &pcfg_pull_none>;
  };
 };

 spdif {
  /omit-if-no-ref/
  spdifm0_tx: spdifm0-tx {
   rockchip,pins =

    <1 4 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  spdifm1_tx: spdifm1-tx {
   rockchip,pins =

    <3 21 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  spdifm2_tx: spdifm2-tx {
   rockchip,pins =

    <4 20 2 &pcfg_pull_none>;
  };
 };

 spi0 {
  /omit-if-no-ref/
  spi0m0_pins: spi0m0-pins {
   rockchip,pins =

    <0 13 2 &pcfg_pull_none>,

    <0 21 2 &pcfg_pull_none>,

    <0 14 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  spi0m0_cs0: spi0m0-cs0 {
   rockchip,pins =

    <0 22 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  spi0m0_cs1: spi0m0-cs1 {
   rockchip,pins =

    <0 20 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  spi0m1_pins: spi0m1-pins {
   rockchip,pins =

    <2 27 3 &pcfg_pull_none>,

    <2 24 3 &pcfg_pull_none>,

    <2 25 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  spi0m1_cs0: spi0m1-cs0 {
   rockchip,pins =

    <2 26 3 &pcfg_pull_none>;
  };
 };

 spi1 {
  /omit-if-no-ref/
  spi1m0_pins: spi1m0-pins {
   rockchip,pins =

    <2 13 3 &pcfg_pull_none>,

    <2 14 3 &pcfg_pull_none>,

    <2 15 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  spi1m0_cs0: spi1m0-cs0 {
   rockchip,pins =

    <2 16 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  spi1m0_cs1: spi1m0-cs1 {
   rockchip,pins =

    <2 22 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  spi1m1_pins: spi1m1-pins {
   rockchip,pins =

    <3 19 3 &pcfg_pull_none>,

    <3 18 3 &pcfg_pull_none>,

    <3 17 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  spi1m1_cs0: spi1m1-cs0 {
   rockchip,pins =

    <3 1 3 &pcfg_pull_none>;
  };
 };

 spi2 {
  /omit-if-no-ref/
  spi2m0_pins: spi2m0-pins {
   rockchip,pins =

    <2 17 4 &pcfg_pull_none>,

    <2 18 4 &pcfg_pull_none>,

    <2 19 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  spi2m0_cs0: spi2m0-cs0 {
   rockchip,pins =

    <2 20 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  spi2m0_cs1: spi2m0-cs1 {
   rockchip,pins =

    <2 21 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  spi2m1_pins: spi2m1-pins {
   rockchip,pins =

    <3 0 3 &pcfg_pull_none>,

    <2 31 3 &pcfg_pull_none>,

    <2 30 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  spi2m1_cs0: spi2m1-cs0 {
   rockchip,pins =

    <2 29 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  spi2m1_cs1: spi2m1-cs1 {
   rockchip,pins =

    <2 28 3 &pcfg_pull_none>;
  };
 };

 spi3 {
  /omit-if-no-ref/
  spi3m0_pins: spi3m0-pins {
   rockchip,pins =

    <4 11 4 &pcfg_pull_none>,

    <4 8 4 &pcfg_pull_none>,

    <4 10 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  spi3m0_cs0: spi3m0-cs0 {
   rockchip,pins =

    <4 6 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  spi3m0_cs1: spi3m0-cs1 {
   rockchip,pins =

    <4 7 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  spi3m1_pins: spi3m1-pins {
   rockchip,pins =

    <4 18 2 &pcfg_pull_none>,

    <4 21 2 &pcfg_pull_none>,

    <4 19 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  spi3m1_cs0: spi3m1-cs0 {
   rockchip,pins =

    <4 22 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  spi3m1_cs1: spi3m1-cs1 {
   rockchip,pins =

    <4 25 2 &pcfg_pull_none>;
  };
 };

 tsadc {
  /omit-if-no-ref/
  tsadcm0_shut: tsadcm0-shut {
   rockchip,pins =

    <0 1 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  tsadcm1_shut: tsadcm1-shut {
   rockchip,pins =

    <0 2 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  tsadc_shutorg: tsadc-shutorg {
   rockchip,pins =

    <0 1 2 &pcfg_pull_none>;
  };
 };

 uart0 {
  /omit-if-no-ref/
  uart0_xfer: uart0-xfer {
   rockchip,pins =

    <0 16 3 &pcfg_pull_up>,

    <0 17 3 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart0_ctsn: uart0-ctsn {
   rockchip,pins =

    <0 23 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart0_rtsn: uart0-rtsn {
   rockchip,pins =

    <0 20 3 &pcfg_pull_none>;
  };
 };

 uart1 {
  /omit-if-no-ref/
  uart1m0_xfer: uart1m0-xfer {
   rockchip,pins =

    <2 11 2 &pcfg_pull_up>,

    <2 12 2 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart1m0_ctsn: uart1m0-ctsn {
   rockchip,pins =

    <2 14 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart1m0_rtsn: uart1m0-rtsn {
   rockchip,pins =

    <2 13 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart1m1_xfer: uart1m1-xfer {
   rockchip,pins =

    <3 31 4 &pcfg_pull_up>,

    <3 30 4 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart1m1_ctsn: uart1m1-ctsn {
   rockchip,pins =

    <4 17 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart1m1_rtsn: uart1m1-rtsn {
   rockchip,pins =

    <4 14 4 &pcfg_pull_none>;
  };
 };

 uart2 {
  /omit-if-no-ref/
  uart2m0_xfer: uart2m0-xfer {
   rockchip,pins =

    <0 24 1 &pcfg_pull_up>,

    <0 25 1 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart2m1_xfer: uart2m1-xfer {
   rockchip,pins =

    <1 30 2 &pcfg_pull_up>,

    <1 29 2 &pcfg_pull_up>;
  };
 };

 uart3 {
  /omit-if-no-ref/
  uart3m0_xfer: uart3m0-xfer {
   rockchip,pins =

    <1 0 2 &pcfg_pull_up>,

    <1 1 2 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart3m0_ctsn: uart3m0-ctsn {
   rockchip,pins =

    <1 3 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart3m0_rtsn: uart3m0-rtsn {
   rockchip,pins =

    <1 2 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart3m1_xfer: uart3m1-xfer {
   rockchip,pins =

    <3 16 4 &pcfg_pull_up>,

    <3 15 4 &pcfg_pull_up>;
  };
 };

 uart4 {
  /omit-if-no-ref/
  uart4m0_xfer: uart4m0-xfer {
   rockchip,pins =

    <1 4 2 &pcfg_pull_up>,

    <1 6 2 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart4m0_ctsn: uart4m0-ctsn {
   rockchip,pins =

    <1 7 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart4m0_rtsn: uart4m0-rtsn {
   rockchip,pins =

    <1 5 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart4m1_xfer: uart4m1-xfer {
   rockchip,pins =

    <3 9 4 &pcfg_pull_up>,

    <3 10 4 &pcfg_pull_up>;
  };
 };

 uart5 {
  /omit-if-no-ref/
  uart5m0_xfer: uart5m0-xfer {
   rockchip,pins =

    <2 1 3 &pcfg_pull_up>,

    <2 2 3 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart5m0_ctsn: uart5m0-ctsn {
   rockchip,pins =

    <1 31 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart5m0_rtsn: uart5m0-rtsn {
   rockchip,pins =

    <2 0 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart5m1_xfer: uart5m1-xfer {
   rockchip,pins =

    <3 19 4 &pcfg_pull_up>,

    <3 18 4 &pcfg_pull_up>;
  };
 };

 uart6 {
  /omit-if-no-ref/
  uart6m0_xfer: uart6m0-xfer {
   rockchip,pins =

    <2 3 3 &pcfg_pull_up>,

    <2 4 3 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart6m0_ctsn: uart6m0-ctsn {
   rockchip,pins =

    <2 16 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart6m0_rtsn: uart6m0-rtsn {
   rockchip,pins =

    <2 15 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart6m1_xfer: uart6m1-xfer {
   rockchip,pins =

    <1 30 3 &pcfg_pull_up>,

    <1 29 3 &pcfg_pull_up>;
  };
 };

 uart7 {
  /omit-if-no-ref/
  uart7m0_xfer: uart7m0-xfer {
   rockchip,pins =

    <2 5 3 &pcfg_pull_up>,

    <2 6 3 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart7m0_ctsn: uart7m0-ctsn {
   rockchip,pins =

    <2 18 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart7m0_rtsn: uart7m0-rtsn {
   rockchip,pins =

    <2 17 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart7m1_xfer: uart7m1-xfer {
   rockchip,pins =

    <3 21 4 &pcfg_pull_up>,

    <3 20 4 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart7m2_xfer: uart7m2-xfer {
   rockchip,pins =

    <4 3 4 &pcfg_pull_up>,

    <4 2 4 &pcfg_pull_up>;
  };
 };

 uart8 {
  /omit-if-no-ref/
  uart8m0_xfer: uart8m0-xfer {
   rockchip,pins =

    <2 22 2 &pcfg_pull_up>,

    <2 21 3 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart8m0_ctsn: uart8m0-ctsn {
   rockchip,pins =

    <2 10 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart8m0_rtsn: uart8m0-rtsn {
   rockchip,pins =

    <2 9 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart8m1_xfer: uart8m1-xfer {
   rockchip,pins =

    <3 0 4 &pcfg_pull_up>,

    <2 31 4 &pcfg_pull_up>;
  };
 };

 uart9 {
  /omit-if-no-ref/
  uart9m0_xfer: uart9m0-xfer {
   rockchip,pins =

    <2 7 3 &pcfg_pull_up>,

    <2 8 3 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart9m0_ctsn: uart9m0-ctsn {
   rockchip,pins =

    <2 20 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart9m0_rtsn: uart9m0-rtsn {
   rockchip,pins =

    <2 19 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart9m1_xfer: uart9m1-xfer {
   rockchip,pins =

    <4 22 4 &pcfg_pull_up>,

    <4 21 4 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart9m2_xfer: uart9m2-xfer {
   rockchip,pins =

    <4 5 4 &pcfg_pull_up>,

    <4 4 4 &pcfg_pull_up>;
  };
 };

 vop {
  /omit-if-no-ref/
  vopm0_pins: vopm0-pins {
   rockchip,pins =

    <0 19 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  vopm1_pins: vopm1-pins {
   rockchip,pins =

    <3 20 2 &pcfg_pull_none>;
  };
 };
};




&pinctrl {
 spi0-hs {
  /omit-if-no-ref/
  spi0m0_pins_hs: spi0m0-pins {
   rockchip,pins =

    <0 13 2 &pcfg_pull_up_drv_level_1>,

    <0 21 2 &pcfg_pull_up_drv_level_1>,

    <0 14 2 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi0m0_cs0_hs: spi0m0-cs0 {
   rockchip,pins =

    <0 22 2 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi0m0_cs1_hs: spi0m0-cs1 {
   rockchip,pins =

    <0 20 2 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi0m1_pins_hs: spi0m1-pins {
   rockchip,pins =

    <2 27 3 &pcfg_pull_up_drv_level_1>,

    <2 24 3 &pcfg_pull_up_drv_level_1>,

    <2 25 3 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi0m1_cs0_hs: spi0m1-cs0 {
   rockchip,pins =

    <2 26 3 &pcfg_pull_up_drv_level_1>;
  };
 };

 spi1-hs {
  /omit-if-no-ref/
  spi1m0_pins_hs: spi1m0-pins {
   rockchip,pins =

    <2 13 3 &pcfg_pull_up_drv_level_1>,

    <2 14 3 &pcfg_pull_up_drv_level_1>,

    <2 15 4 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi1m0_cs0_hs: spi1m0-cs0 {
   rockchip,pins =

    <2 16 4 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi1m0_cs1_hs: spi1m0-cs1 {
   rockchip,pins =

    <2 22 3 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi1m1_pins_hs: spi1m1-pins {
   rockchip,pins =

    <3 19 3 &pcfg_pull_up_drv_level_1>,

    <3 18 3 &pcfg_pull_up_drv_level_1>,

    <3 17 3 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi1m1_cs0_hs: spi1m1-cs0 {
   rockchip,pins =

    <3 1 3 &pcfg_pull_up_drv_level_1>;
  };
 };

 spi2-hs {
  /omit-if-no-ref/
  spi2m0_pins_hs: spi2m0-pins {
   rockchip,pins =

    <2 17 4 &pcfg_pull_up_drv_level_1>,

    <2 18 4 &pcfg_pull_up_drv_level_1>,

    <2 19 4 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi2m0_cs0_hs: spi2m0-cs0 {
   rockchip,pins =

    <2 20 4 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi2m0_cs1_hs: spi2m0-cs1 {
   rockchip,pins =

    <2 21 4 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi2m1_pins_hs: spi2m1-pins {
   rockchip,pins =

    <3 0 3 &pcfg_pull_up_drv_level_1>,

    <2 31 3 &pcfg_pull_up_drv_level_1>,

    <2 30 3 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi2m1_cs0_hs: spi2m1-cs0 {
   rockchip,pins =

    <2 29 3 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi2m1_cs1_hs: spi2m1-cs1 {
   rockchip,pins =

    <2 28 3 &pcfg_pull_up_drv_level_1>;
  };
 };

 spi3-hs {
  /omit-if-no-ref/
  spi3m0_pins_hs: spi3m0-pins {
   rockchip,pins =

    <4 11 4 &pcfg_pull_up_drv_level_1>,

    <4 8 4 &pcfg_pull_up_drv_level_1>,

    <4 10 4 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi3m0_cs0_hs: spi3m0-cs0 {
   rockchip,pins =

    <4 6 4 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi3m0_cs1_hs: spi3m0-cs1 {
   rockchip,pins =

    <4 7 4 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi3m1_pins_hs: spi3m1-pins {
   rockchip,pins =

    <4 18 2 &pcfg_pull_up_drv_level_1>,

    <4 21 2 &pcfg_pull_up_drv_level_1>,

    <4 19 2 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi3m1_cs0_hs: spi3m1-cs0 {
   rockchip,pins =

    <4 22 2 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi3m1_cs1_hs: spi3m1-cs1 {
   rockchip,pins =

    <4 25 2 &pcfg_pull_up_drv_level_1>;
  };
 };

 gmac-txd-level3 {
  /omit-if-no-ref/
  gmac0_tx_bus2_level3: gmac0-tx-bus2-level3 {
   rockchip,pins =

    <2 11 1 &pcfg_pull_none_drv_level_3>,

    <2 12 1 &pcfg_pull_none_drv_level_3>,

    <2 13 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac0_rgmii_bus_level3: gmac0-rgmii-bus-level3 {
   rockchip,pins =

    <2 3 2 &pcfg_pull_none>,

    <2 4 2 &pcfg_pull_none>,

    <2 6 2 &pcfg_pull_none_drv_level_3>,

    <2 7 2 &pcfg_pull_none_drv_level_3>;
  };

  /omit-if-no-ref/
  gmac1m0_tx_bus2_level3: gmac1m0-tx-bus2-level3 {
   rockchip,pins =

    <3 13 3 &pcfg_pull_none_drv_level_3>,

    <3 14 3 &pcfg_pull_none_drv_level_3>,

    <3 15 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1m0_rgmii_bus_level3: gmac1m0-rgmii-bus-level3 {
   rockchip,pins =

    <3 4 3 &pcfg_pull_none>,

    <3 5 3 &pcfg_pull_none>,

    <3 2 3 &pcfg_pull_none_drv_level_3>,

    <3 3 3 &pcfg_pull_none_drv_level_3>;
  };

  /omit-if-no-ref/
  gmac1m1_tx_bus2_level3: gmac1m1-tx-bus2-level3 {
   rockchip,pins =

    <4 4 3 &pcfg_pull_none_drv_level_3>,

    <4 5 3 &pcfg_pull_none_drv_level_3>,

    <4 6 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1m1_rgmii_bus_level3: gmac1m1-rgmii-bus-level3 {
   rockchip,pins =

    <4 1 3 &pcfg_pull_none>,

    <4 2 3 &pcfg_pull_none>,

    <3 30 3 &pcfg_pull_none_drv_level_3>,

    <3 31 3 &pcfg_pull_none_drv_level_3>;
  };
 };

 gmac-txc-level2 {
  /omit-if-no-ref/
  gmac0_rgmii_clk_level2: gmac0-rgmii-clk-level2 {
   rockchip,pins =

    <2 5 2 &pcfg_pull_none>,

    <2 8 2 &pcfg_pull_none_drv_level_2>;
  };

  /omit-if-no-ref/
  gmac1m0_rgmii_clk_level2: gmac1m0-rgmii-clk-level2 {
   rockchip,pins =

    <3 7 3 &pcfg_pull_none>,

    <3 6 3 &pcfg_pull_none_drv_level_2>;
  };

  /omit-if-no-ref/
  gmac1m1_rgmii_clk_level2: gmac1m1-rgmii-clk-level2 {
   rockchip,pins =

    <4 3 3 &pcfg_pull_none>,

    <4 0 3 &pcfg_pull_none_drv_level_2>;
  };
 };

 tsadc {
  /omit-if-no-ref/
  tsadc_pin: tsadc-pin {
   rockchip,pins =

    <0 1 0 &pcfg_pull_none>;
  };
 };

 lcdc {
  /omit-if-no-ref/
  lcdc_clock: lcdc-clock {
   rockchip,pins =

    <3 0 1 &pcfg_pull_none>,

    <3 19 1 &pcfg_pull_none>,

    <3 17 1 &pcfg_pull_none>,

    <3 18 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  lcdc_data16: lcdc-data16 {
   rockchip,pins =

    <2 27 1 &pcfg_pull_none>,

    <2 28 1 &pcfg_pull_none>,

    <2 29 1 &pcfg_pull_none>,

    <2 30 1 &pcfg_pull_none>,

    <2 31 1 &pcfg_pull_none>,

    <3 3 1 &pcfg_pull_none>,

    <3 4 1 &pcfg_pull_none>,

    <3 5 1 &pcfg_pull_none>,

    <3 6 1 &pcfg_pull_none>,

    <3 7 1 &pcfg_pull_none>,

    <3 8 1 &pcfg_pull_none>,

    <3 12 1 &pcfg_pull_none>,

    <3 13 1 &pcfg_pull_none>,

    <3 14 1 &pcfg_pull_none>,

    <3 15 1 &pcfg_pull_none>,

    <3 16 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  lcdc_data18: lcdc-data18 {
   rockchip,pins =

    <2 26 1 &pcfg_pull_none>,

    <2 27 1 &pcfg_pull_none>,

    <2 28 1 &pcfg_pull_none>,

    <2 29 1 &pcfg_pull_none>,

    <2 30 1 &pcfg_pull_none>,

    <2 31 1 &pcfg_pull_none>,

    <3 3 1 &pcfg_pull_none>,

    <3 4 1 &pcfg_pull_none>,

    <3 5 1 &pcfg_pull_none>,

    <3 6 1 &pcfg_pull_none>,

    <3 7 1 &pcfg_pull_none>,

    <3 8 1 &pcfg_pull_none>,

    <3 11 1 &pcfg_pull_none>,

    <3 12 1 &pcfg_pull_none>,

    <3 13 1 &pcfg_pull_none>,

    <3 14 1 &pcfg_pull_none>,

    <3 15 1 &pcfg_pull_none>,

    <3 16 1 &pcfg_pull_none>;
  };
 };

};
# 1880 "arch/arm64/boot/dts/rockchip/rk356x.dtsi" 2
# 4 "arch/arm64/boot/dts/rockchip/rk3566.dtsi" 2

/ {
 compatible = "rockchip,rk3566";
};

&pipegrf {
 compatible = "rockchip,rk3566-pipe-grf", "syscon";
};

&power {
 power-domain@15 {
  reg = <15>;
  clocks = <&cru 127>;
  pm_qos = <&qos_pcie2x1>,
    <&qos_sata1>,
    <&qos_sata2>,
    <&qos_usb3_0>,
    <&qos_usb3_1>;
  #power-domain-cells = <0>;
 };
};

&usb_host0_xhci {
 phys = <&usb2phy0_otg>;
 phy-names = "usb2-phy";
 extcon = <&usb2phy0>;
 maximum-speed = "high-speed";
};

&vop {
 compatible = "rockchip,rk3566-vop";
};
# 9 "arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts" 2

/ {
 model = "Pine64 RK3566 Quartz64-B Board";
 compatible = "pine64,quartz64-b", "rockchip,rk3566";

 aliases {
  ethernet0 = &gmac1;
  mmc0 = &sdmmc0;
  mmc1 = &sdhci;
  mmc2 = &sdmmc1;
 };

 chosen: chosen {
  stdout-path = "serial2:1500000n8";
 };

 gmac1_clkin: external-gmac1-clock {
  compatible = "fixed-clock";
  clock-frequency = <125000000>;
  clock-output-names = "gmac1_clkin";
  #clock-cells = <0>;
 };

 hdmi-con {
  compatible = "hdmi-connector";
  type = "a";

  port {
   hdmi_con_in: endpoint {
    remote-endpoint = <&hdmi_out_con>;
   };
  };
 };

 leds {
  compatible = "gpio-leds";

  led-user {
   label = "user-led";
   default-state = "on";
   gpios = <&gpio0 0 0>;
   linux,default-trigger = "heartbeat";
   pinctrl-names = "default";
   pinctrl-0 = <&user_led_enable_h>;
   retain-state-suspended;
  };
 };

 sound {
  compatible = "simple-audio-card";
  simple-audio-card,format = "i2s";
  simple-audio-card,name = "Analog RK809";
  simple-audio-card,mclk-fs = <256>;

  simple-audio-card,cpu {
   sound-dai = <&i2s1_8ch>;
  };

  simple-audio-card,codec {
   sound-dai = <&rk809>;
  };
 };

 sdio_pwrseq: sdio-pwrseq {
  status = "okay";
  compatible = "mmc-pwrseq-simple";
  clocks = <&rk809 1>;
  clock-names = "ext_clock";
  pinctrl-names = "default";
  pinctrl-0 = <&wifi_enable_h>;
  reset-gpios = <&gpio0 16 1>;
  post-power-on-delay-ms = <100>;
  power-off-delay-us = <5000000>;
 };

 vcc3v3_pcie_p: vcc3v3-pcie-p-regulator {
  compatible = "regulator-fixed";
  enable-active-high;
  gpio = <&gpio0 6 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&pcie_enable_h>;
  regulator-name = "vcc3v3_pcie_p";
  regulator-min-microvolt = <3300000>;
  regulator-max-microvolt = <3300000>;
  vin-supply = <&vcc_3v3>;
 };

 vcc5v0_in: vcc5v0-in-regulator {
  compatible = "regulator-fixed";
  regulator-name = "vcc5v0_in";
  regulator-always-on;
  regulator-boot-on;
  regulator-min-microvolt = <5000000>;
  regulator-max-microvolt = <5000000>;
 };

 vcc5v0_sys: vcc5v0-sys-regulator {
  compatible = "regulator-fixed";
  regulator-name = "vcc5v0_sys";
  regulator-always-on;
  regulator-boot-on;
  regulator-min-microvolt = <5000000>;
  regulator-max-microvolt = <5000000>;
  vin-supply = <&vcc5v0_in>;
 };

 vcc3v3_sys: vcc3v3-sys-regulator {
  compatible = "regulator-fixed";
  regulator-name = "vcc3v3_sys";
  regulator-min-microvolt = <3300000>;
  regulator-max-microvolt = <3300000>;
  regulator-always-on;
  vin-supply = <&vcc5v0_sys>;
 };

 vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
  compatible = "regulator-fixed";
  regulator-name = "vcc5v0_usb30_host";
  enable-active-high;
  gpio = <&gpio0 21 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&vcc5v0_usb30_host_en_h>;
  regulator-always-on;
  regulator-min-microvolt = <5000000>;
  regulator-max-microvolt = <5000000>;
  vin-supply = <&vcc5v0_sys>;
 };

 vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
  compatible = "regulator-fixed";
  regulator-name = "vcc5v0_usb_otg";
  enable-active-high;
  gpio = <&gpio0 22 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&vcc5v0_usb_otg_en_h>;
  regulator-always-on;
  regulator-min-microvolt = <5000000>;
  regulator-max-microvolt = <5000000>;
  vin-supply = <&vcc5v0_sys>;
 };
};

&combphy1 {
 status = "okay";
};

&combphy2 {
 status = "okay";
};

&cpu0 {
 cpu-supply = <&vdd_cpu>;
};

&cpu1 {
 cpu-supply = <&vdd_cpu>;
};

&cpu2 {
 cpu-supply = <&vdd_cpu>;
};

&cpu3 {
 cpu-supply = <&vdd_cpu>;
};

&gmac1 {
 assigned-clocks = <&cru 393>, <&cru 391>, <&cru 390>;
 assigned-clock-parents = <&cru 391>, <&cru 390>, <&gmac1_clkin>;
 clock_in_out = "input";
 phy-mode = "rgmii";
 phy-supply = <&vcc_3v3>;
 pinctrl-names = "default";
 pinctrl-0 = <&gmac1m1_miim
       &gmac1m1_tx_bus2
       &gmac1m1_rx_bus2
       &gmac1m1_rgmii_clk
       &gmac1m1_clkinout
       &gmac1m1_rgmii_bus>;
 snps,reset-gpio = <&gpio3 16 1>;
 snps,reset-active-low;

 snps,reset-delays-us = <0 20000 100000>;
 tx_delay = <0x4f>;
 rx_delay = <0x24>;
 phy-handle = <&rgmii_phy1>;
 status = "okay";
};

&gpu {
 mali-supply = <&vdd_gpu>;
 status = "okay";
};

&hdmi {
 avdd-0v9-supply = <&vdda0v9_image>;
 avdd-1v8-supply = <&vcca1v8_image>;
 status = "okay";
};

&hdmi_in {
 hdmi_in_vp0: endpoint {
  remote-endpoint = <&vp0_out_hdmi>;
 };
};

&hdmi_out {
 hdmi_out_con: endpoint {
  remote-endpoint = <&hdmi_con_in>;
 };
};

&hdmi_sound {
 status = "okay";
};

&i2c0 {
 status = "okay";

 vdd_cpu: regulator@1c {
  compatible = "tcs,tcs4525";
  reg = <0x1c>;
  fcs,suspend-voltage-selector = <1>;
  regulator-name = "vdd_cpu";
  regulator-min-microvolt = <800000>;
  regulator-max-microvolt = <1150000>;
  regulator-ramp-delay = <2300>;
  regulator-always-on;
  regulator-boot-on;
  vin-supply = <&vcc5v0_sys>;

  regulator-state-mem {
   regulator-off-in-suspend;
  };
 };

 rk809: pmic@20 {
  compatible = "rockchip,rk809";
  reg = <0x20>;
  interrupt-parent = <&gpio0>;
  interrupts = <3 8>;
  assigned-clocks = <&cru 72>;
  assigned-clock-parents = <&cru 406>;
  clock-names = "mclk";
  clocks = <&cru 72>;
  clock-output-names = "rk808-clkout1", "rk808-clkout2";

  pinctrl-names = "default";
  pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
  rockchip,system-power-controller;
  #sound-dai-cells = <0>;
  wakeup-source;
  #clock-cells = <1>;

  vcc1-supply = <&vcc3v3_sys>;
  vcc2-supply = <&vcc3v3_sys>;
  vcc3-supply = <&vcc3v3_sys>;
  vcc4-supply = <&vcc3v3_sys>;
  vcc5-supply = <&vcc3v3_sys>;
  vcc6-supply = <&vcc3v3_sys>;
  vcc7-supply = <&vcc3v3_sys>;
  vcc8-supply = <&vcc3v3_sys>;
  vcc9-supply = <&vcc3v3_sys>;

  regulators {
   vdd_log: DCDC_REG1 {
    regulator-name = "vdd_log";
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <500000>;
    regulator-max-microvolt = <1350000>;
    regulator-ramp-delay = <6001>;

    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <900000>;
    };
   };

   vdd_gpu: DCDC_REG2 {
    regulator-name = "vdd_gpu";
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <900000>;
    regulator-max-microvolt = <1350000>;
    regulator-ramp-delay = <6001>;

    regulator-state-mem {
     regulator-off-in-suspend;
     regulator-suspend-microvolt = <900000>;
    };
   };

   vcc_ddr: DCDC_REG3 {
    regulator-name = "vcc_ddr";
    regulator-always-on;
    regulator-boot-on;
    regulator-initial-mode = <0x2>;
    regulator-state-mem {
     regulator-on-in-suspend;
    };
   };

   vdd_npu: DCDC_REG4 {
    regulator-name = "vdd_npu";
    regulator-min-microvolt = <900000>;
    regulator-max-microvolt = <1350000>;
    regulator-initial-mode = <0x2>;
    regulator-state-mem {
     regulator-off-in-suspend;
    };
   };

   vcc_1v8: DCDC_REG5 {
    regulator-name = "vcc_1v8";
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <1800000>;

    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <1800000>;
    };
   };

   vdda0v9_image: LDO_REG1 {
    regulator-name = "vdda0v9_image";
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <900000>;
    regulator-max-microvolt = <900000>;

    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <900000>;
    };
   };

   vdda_0v9: LDO_REG2 {
    regulator-name = "vdda_0v9";
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <900000>;
    regulator-max-microvolt = <900000>;

    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <900000>;
    };
   };

   vdda0v9_pmu: LDO_REG3 {
    regulator-name = "vdda0v9_pmu";
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <900000>;
    regulator-max-microvolt = <900000>;
    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <900000>;
    };
   };

   vccio_acodec: LDO_REG4 {
    regulator-name = "vccio_acodec";
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <3300000>;
    regulator-max-microvolt = <3300000>;

    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <3300000>;

    };
   };

   vccio_sd: LDO_REG5 {
    regulator-name = "vccio_sd";
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <3300000>;

    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <3300000>;
    };
   };

   vcc3v3_pmu: LDO_REG6 {
    regulator-name = "vcc3v3_pmu";
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <3300000>;
    regulator-max-microvolt = <3300000>;

    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <3300000>;
    };
   };

   vcca_1v8: LDO_REG7 {
    regulator-name = "vcca_1v8";
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <1800000>;

    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <1800000>;
    };
   };

   vcca1v8_pmu: LDO_REG8 {
    regulator-name = "vcca1v8_pmu";
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <1800000>;

    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <1800000>;
    };
   };

   vcca1v8_image: LDO_REG9 {
    regulator-name = "vcca1v8_image";
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <1800000>;

    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <1800000>;
    };
   };

   vcc_3v3: SWITCH_REG1 {
    regulator-boot-on;
    regulator-name = "vcc_3v3";
   };

   vcc3v3_sd: SWITCH_REG2 {
    regulator-name = "vcc3v3_sd";
   };
  };
 };
};


&i2c2 {
 pinctrl-names = "default";
 pinctrl-0 = <&i2c2m1_xfer>;
 status = "okay";
};


&i2c3 {
 pinctrl-names = "default";
 pinctrl-0 = <&i2c3m1_xfer>;
 status = "okay";
};






&i2c4 {
 status = "okay";
};






&i2c5 {
 status = "disabled";
};

&i2s0_8ch {
 status = "okay";
};

&i2s1_8ch {
 pinctrl-names = "default";
 pinctrl-0 = <&i2s1m0_sclktx
       &i2s1m0_lrcktx
       &i2s1m0_sdi0
       &i2s1m0_sdo0>;
 rockchip,trcm-sync-tx-only;
 status = "okay";
};

&mdio1 {
 rgmii_phy1: ethernet-phy@1 {
  compatible = "ethernet-phy-ieee802.3-c22";
  reg = <0x1>;
 };
};

&pcie2x1 {
 pinctrl-names = "default";
 pinctrl-0 = <&pcie_reset_h>;
 reset-gpios = <&gpio1 10 0>;
 vpcie3v3-supply = <&vcc3v3_pcie_p>;
 status = "okay";
};

&pinctrl {
 bt {
  bt_enable_h: bt-enable-h {
   rockchip,pins = <0 17 0 &pcfg_pull_none>;
  };

  bt_host_wake_l: bt-host-wake-l {
   rockchip,pins = <0 11 0 &pcfg_pull_down>;
  };

  bt_wake_l: bt-wake-l {
   rockchip,pins = <0 12 0 &pcfg_pull_none>;
  };
 };

 leds {
  user_led_enable_h: user-led-enable-h {
   rockchip,pins = <0 0 0 &pcfg_pull_none>;
  };
 };

 pcie {
  pcie_enable_h: pcie-enable-h {
   rockchip,pins = <0 6 0 &pcfg_pull_none>;
  };

  pcie_reset_h: pcie-reset-h {
   rockchip,pins = <1 10 0 &pcfg_pull_none>;
  };
 };

 pmic {
  pmic_int: pmic_int {
   rockchip,pins =
    <0 3 0 &pcfg_pull_up>;
  };
 };

 sdio-pwrseq {
  wifi_enable_h: wifi-enable-h {
   rockchip,pins = <0 16 0 &pcfg_pull_none>;
  };
 };

 usb {
  vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h {
   rockchip,pins = <0 21 0 &pcfg_pull_none>;
  };

  vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h {
   rockchip,pins = <0 22 0 &pcfg_pull_none>;
  };
 };
};

&pmu_io_domains {
 status = "okay";
 pmuio1-supply = <&vcc3v3_pmu>;
 pmuio2-supply = <&vcca1v8_pmu>;
 vccio1-supply = <&vccio_acodec>;
 vccio2-supply = <&vcc_1v8>;
 vccio3-supply = <&vccio_sd>;
 vccio4-supply = <&vcca1v8_pmu>;
 vccio5-supply = <&vcc_3v3>;
 vccio6-supply = <&vcc_3v3>;
 vccio7-supply = <&vcc_3v3>;
};

&saradc {
 vref-supply = <&vcca_1v8>;
 status = "okay";
};

&sdhci {
 bus-width = <8>;
 mmc-hs200-1_8v;
 non-removable;
 vmmc-supply = <&vcc_3v3>;
 vqmmc-supply = <&vcc_1v8>;
 status = "okay";
};

&sdmmc0 {
 bus-width = <4>;
 cap-sd-highspeed;
 cd-gpios = <&gpio0 4 1>;
 disable-wp;
 pinctrl-names = "default";
 pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
 sd-uhs-sdr50;
 vmmc-supply = <&vcc3v3_sd>;
 vqmmc-supply = <&vccio_sd>;
 status = "okay";
};

&sdmmc1 {
 bus-width = <4>;
 cap-sd-highspeed;
 cap-sdio-irq;
 keep-power-in-suspend;
 mmc-pwrseq = <&sdio_pwrseq>;
 non-removable;
 pinctrl-names = "default";
 pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
 vmmc-supply = <&vcc3v3_sys>;
 vqmmc-supply = <&vcca1v8_pmu>;
 status = "okay";
};

&sfc {
 pinctrl-0 = <&fspi_pins>;
 pinctrl-names = "default";
 #address-cells = <1>;
 #size-cells = <0>;
 status = "okay";

 flash@0 {
  compatible = "jedec,spi-nor";
  reg = <0>;
  spi-max-frequency = <24000000>;
  spi-rx-bus-width = <4>;
  spi-tx-bus-width = <1>;
 };
};

&tsadc {
 status = "okay";
};

&uart1 {
 pinctrl-names = "default";
 pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
 status = "okay";
 uart-has-rtscts;

 bluetooth {
  compatible = "brcm,bcm4345c5";
  clocks = <&rk809 1>;
  clock-names = "lpo";
  device-wakeup-gpios = <&gpio0 12 0>;
  host-wakeup-gpios = <&gpio0 11 0>;
  shutdown-gpios = <&gpio0 17 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
  vbat-supply = <&vcc3v3_sys>;
  vddio-supply = <&vcca1v8_pmu>;
 };
};






&uart2 {
 status = "okay";
};

&usb2phy0_host {
 phy-supply = <&vcc5v0_usb30_host>;
 status = "okay";
};

&usb2phy0_otg {
 phy-supply = <&vcc5v0_usb_otg>;
 status = "okay";
};

&usb2phy1_otg {
 phy-supply = <&vcc5v0_usb30_host>;
 status = "okay";
};

&usb2phy0 {
 status = "okay";
};

&usb2phy1 {
 status = "okay";
};

&usb_host0_xhci {
 status = "okay";
};

&usb_host1_xhci {
 status = "okay";
};

&usb_host0_ehci {
 status = "okay";
};

&usb_host0_ohci {
 status = "okay";
};

&vop {
 assigned-clocks = <&cru 223>, <&cru 224>;
 assigned-clock-parents = <&pmucru 2>, <&cru 5>;
 status = "okay";
};

&vop_mmu {
 status = "okay";
};

&vp0 {
 vp0_out_hdmi: endpoint@2 {
  reg = <2>;
  remote-endpoint = <&hdmi_in_vp0>;
 };
};