# 0 "arch/arm64/boot/dts/rockchip/rk3399-evb.dts"
# 0 "<built-in>"
# 0 "<command-line>"
# 1 "arch/arm64/boot/dts/rockchip/rk3399-evb.dts"





/dts-v1/;
# 1 "./scripts/dtc/include-prefixes/dt-bindings/pwm/pwm.h" 1
# 8 "arch/arm64/boot/dts/rockchip/rk3399-evb.dts" 2
# 1 "arch/arm64/boot/dts/rockchip/rk3399.dtsi" 1





# 1 "./scripts/dtc/include-prefixes/dt-bindings/clock/rk3399-cru.h" 1
# 7 "arch/arm64/boot/dts/rockchip/rk3399.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/gpio/gpio.h" 1
# 8 "arch/arm64/boot/dts/rockchip/rk3399.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h" 1
# 9 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h"
# 1 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/irq.h" 1
# 10 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h" 2
# 9 "arch/arm64/boot/dts/rockchip/rk3399.dtsi" 2

# 1 "./scripts/dtc/include-prefixes/dt-bindings/pinctrl/rockchip.h" 1
# 11 "arch/arm64/boot/dts/rockchip/rk3399.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/power/rk3399-power.h" 1
# 12 "arch/arm64/boot/dts/rockchip/rk3399.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/thermal/thermal.h" 1
# 13 "arch/arm64/boot/dts/rockchip/rk3399.dtsi" 2

/ {
 compatible = "rockchip,rk3399";

 interrupt-parent = <&gic>;
 #address-cells = <2>;
 #size-cells = <2>;

 aliases {
  ethernet0 = &gmac;
  i2c0 = &i2c0;
  i2c1 = &i2c1;
  i2c2 = &i2c2;
  i2c3 = &i2c3;
  i2c4 = &i2c4;
  i2c5 = &i2c5;
  i2c6 = &i2c6;
  i2c7 = &i2c7;
  i2c8 = &i2c8;
  serial0 = &uart0;
  serial1 = &uart1;
  serial2 = &uart2;
  serial3 = &uart3;
  serial4 = &uart4;
 };

 cpus {
  #address-cells = <2>;
  #size-cells = <0>;

  cpu-map {
   cluster0 {
    core0 {
     cpu = <&cpu_l0>;
    };
    core1 {
     cpu = <&cpu_l1>;
    };
    core2 {
     cpu = <&cpu_l2>;
    };
    core3 {
     cpu = <&cpu_l3>;
    };
   };

   cluster1 {
    core0 {
     cpu = <&cpu_b0>;
    };
    core1 {
     cpu = <&cpu_b1>;
    };
   };
  };

  cpu_l0: cpu@0 {
   device_type = "cpu";
   compatible = "arm,cortex-a53";
   reg = <0x0 0x0>;
   enable-method = "psci";
   capacity-dmips-mhz = <485>;
   clocks = <&cru 8>;
   #cooling-cells = <2>;
   dynamic-power-coefficient = <100>;
   cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  };

  cpu_l1: cpu@1 {
   device_type = "cpu";
   compatible = "arm,cortex-a53";
   reg = <0x0 0x1>;
   enable-method = "psci";
   capacity-dmips-mhz = <485>;
   clocks = <&cru 8>;
   #cooling-cells = <2>;
   dynamic-power-coefficient = <100>;
   cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  };

  cpu_l2: cpu@2 {
   device_type = "cpu";
   compatible = "arm,cortex-a53";
   reg = <0x0 0x2>;
   enable-method = "psci";
   capacity-dmips-mhz = <485>;
   clocks = <&cru 8>;
   #cooling-cells = <2>;
   dynamic-power-coefficient = <100>;
   cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  };

  cpu_l3: cpu@3 {
   device_type = "cpu";
   compatible = "arm,cortex-a53";
   reg = <0x0 0x3>;
   enable-method = "psci";
   capacity-dmips-mhz = <485>;
   clocks = <&cru 8>;
   #cooling-cells = <2>;
   dynamic-power-coefficient = <100>;
   cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  };

  cpu_b0: cpu@100 {
   device_type = "cpu";
   compatible = "arm,cortex-a72";
   reg = <0x0 0x100>;
   enable-method = "psci";
   capacity-dmips-mhz = <1024>;
   clocks = <&cru 9>;
   #cooling-cells = <2>;
   dynamic-power-coefficient = <436>;
   cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;

   thermal-idle {
    #cooling-cells = <2>;
    duration-us = <10000>;
    exit-latency-us = <500>;
   };
  };

  cpu_b1: cpu@101 {
   device_type = "cpu";
   compatible = "arm,cortex-a72";
   reg = <0x0 0x101>;
   enable-method = "psci";
   capacity-dmips-mhz = <1024>;
   clocks = <&cru 9>;
   #cooling-cells = <2>;
   dynamic-power-coefficient = <436>;
   cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;

   thermal-idle {
    #cooling-cells = <2>;
    duration-us = <10000>;
    exit-latency-us = <500>;
   };
  };

  idle-states {
   entry-method = "psci";

   CPU_SLEEP: cpu-sleep {
    compatible = "arm,idle-state";
    local-timer-stop;
    arm,psci-suspend-param = <0x0010000>;
    entry-latency-us = <120>;
    exit-latency-us = <250>;
    min-residency-us = <900>;
   };

   CLUSTER_SLEEP: cluster-sleep {
    compatible = "arm,idle-state";
    local-timer-stop;
    arm,psci-suspend-param = <0x1010000>;
    entry-latency-us = <400>;
    exit-latency-us = <500>;
    min-residency-us = <2000>;
   };
  };
 };

 display-subsystem {
  compatible = "rockchip,display-subsystem";
  ports = <&vopl_out>, <&vopb_out>;
 };

 dmc: memory-controller {
  compatible = "rockchip,rk3399-dmc";
  rockchip,pmu = <&pmugrf>;
  devfreq-events = <&dfi>;
  clocks = <&cru 168>;
  clock-names = "dmc_clk";
  status = "disabled";
 };

 pmu_a53 {
  compatible = "arm,cortex-a53-pmu";
  interrupts = <1 7 8 &ppi_cluster0>;
 };

 pmu_a72 {
  compatible = "arm,cortex-a72-pmu";
  interrupts = <1 7 8 &ppi_cluster1>;
 };

 psci {
  compatible = "arm,psci-1.0";
  method = "smc";
 };

 timer {
  compatible = "arm,armv8-timer";
  interrupts = <1 13 8 0>,
        <1 14 8 0>,
        <1 11 8 0>,
        <1 10 8 0>;
  arm,no-tick-in-suspend;
 };

 xin24m: xin24m {
  compatible = "fixed-clock";
  clock-frequency = <24000000>;
  clock-output-names = "xin24m";
  #clock-cells = <0>;
 };

 pcie0: pcie@f8000000 {
  compatible = "rockchip,rk3399-pcie";
  reg = <0x0 0xf8000000 0x0 0x2000000>,
        <0x0 0xfd000000 0x0 0x1000000>;
  reg-names = "axi-base", "apb-base";
  device_type = "pci";
  #address-cells = <3>;
  #size-cells = <2>;
  #interrupt-cells = <1>;
  aspm-no-l0s;
  bus-range = <0x0 0x1f>;
  clocks = <&cru 197>, <&cru 196>,
    <&cru 327>, <&cru 160>;
  clock-names = "aclk", "aclk-perf",
         "hclk", "pm";
  interrupts = <0 49 4 0>,
        <0 50 4 0>,
        <0 51 4 0>;
  interrupt-names = "sys", "legacy", "client";
  interrupt-map-mask = <0 0 0 7>;
  interrupt-map = <0 0 0 1 &pcie0_intc 0>,
    <0 0 0 2 &pcie0_intc 1>,
    <0 0 0 3 &pcie0_intc 2>,
    <0 0 0 4 &pcie0_intc 3>;
  max-link-speed = <1>;
  msi-map = <0x0 &its 0x0 0x1000>;
  phys = <&pcie_phy 0>, <&pcie_phy 1>,
         <&pcie_phy 2>, <&pcie_phy 3>;
  phy-names = "pcie-phy-0", "pcie-phy-1",
       "pcie-phy-2", "pcie-phy-3";
  ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>,
    <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
  resets = <&cru 130>, <&cru 131>,
    <&cru 132>, <&cru 133>,
    <&cru 134>, <&cru 129>,
    <&cru 128>;
  reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
         "pm", "pclk", "aclk";
  status = "disabled";

  pcie0_intc: interrupt-controller {
   interrupt-controller;
   #address-cells = <0>;
   #interrupt-cells = <1>;
  };
 };

 pcie0_ep: pcie-ep@f8000000 {
  compatible = "rockchip,rk3399-pcie-ep";
  reg = <0x0 0xfd000000 0x0 0x1000000>,
        <0x0 0xfa000000 0x0 0x2000000>;
  reg-names = "apb-base", "mem-base";
  clocks = <&cru 197>, <&cru 196>,
    <&cru 327>, <&cru 160>;
  clock-names = "aclk", "aclk-perf",
         "hclk", "pm";
  max-functions = /bits/ 8 <8>;
  num-lanes = <4>;
  resets = <&cru 130>, <&cru 131>,
    <&cru 132>, <&cru 133>,
    <&cru 134>, <&cru 129>,
    <&cru 128>;
  reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
         "pm", "pclk", "aclk";
  phys = <&pcie_phy 0>, <&pcie_phy 1>,
         <&pcie_phy 2>, <&pcie_phy 3>;
  phy-names = "pcie-phy-0", "pcie-phy-1",
       "pcie-phy-2", "pcie-phy-3";
  rockchip,max-outbound-regions = <32>;
  pinctrl-names = "default";
  pinctrl-0 = <&pcie_clkreqnb_cpm>;
  status = "disabled";
 };

 gmac: ethernet@fe300000 {
  compatible = "rockchip,rk3399-gmac";
  reg = <0x0 0xfe300000 0x0 0x10000>;
  interrupts = <0 12 4 0>;
  interrupt-names = "macirq";
  clocks = <&cru 105>, <&cru 103>,
    <&cru 104>, <&cru 102>,
    <&cru 106>, <&cru 213>,
    <&cru 358>;
  clock-names = "stmmaceth", "mac_clk_rx",
         "mac_clk_tx", "clk_mac_ref",
         "clk_mac_refout", "aclk_mac",
         "pclk_mac";
  power-domains = <&power 22>;
  resets = <&cru 137>;
  reset-names = "stmmaceth";
  rockchip,grf = <&grf>;
  snps,txpbl = <0x4>;
  status = "disabled";
 };

 sdio0: mmc@fe310000 {
  compatible = "rockchip,rk3399-dw-mshc",
        "rockchip,rk3288-dw-mshc";
  reg = <0x0 0xfe310000 0x0 0x4000>;
  interrupts = <0 64 4 0>;
  max-frequency = <150000000>;
  clocks = <&cru 494>, <&cru 77>,
    <&cru 156>, <&cru 157>;
  clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  fifo-depth = <0x100>;
  power-domains = <&power 28>;
  resets = <&cru 121>;
  reset-names = "reset";
  status = "disabled";
 };

 sdmmc: mmc@fe320000 {
  compatible = "rockchip,rk3399-dw-mshc",
        "rockchip,rk3288-dw-mshc";
  reg = <0x0 0xfe320000 0x0 0x4000>;
  interrupts = <0 65 4 0>;
  max-frequency = <150000000>;
  assigned-clocks = <&cru 461>;
  assigned-clock-rates = <200000000>;
  clocks = <&cru 462>, <&cru 76>,
    <&cru 154>, <&cru 155>;
  clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  fifo-depth = <0x100>;
  power-domains = <&power 27>;
  resets = <&cru 122>;
  reset-names = "reset";
  status = "disabled";
 };

 sdhci: mmc@fe330000 {
  compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
  reg = <0x0 0xfe330000 0x0 0x10000>;
  interrupts = <0 11 4 0>;
  arasan,soc-ctl-syscon = <&grf>;
  assigned-clocks = <&cru 78>;
  assigned-clock-rates = <200000000>;
  clocks = <&cru 78>, <&cru 240>;
  clock-names = "clk_xin", "clk_ahb";
  clock-output-names = "emmc_cardclock";
  #clock-cells = <0>;
  phys = <&emmc_phy>;
  phy-names = "phy_arasan";
  power-domains = <&power 23>;
  disable-cqe-dcmd;
  status = "disabled";
 };

 usb_host0_ehci: usb@fe380000 {
  compatible = "generic-ehci";
  reg = <0x0 0xfe380000 0x0 0x20000>;
  interrupts = <0 26 4 0>;
  clocks = <&cru 456>, <&cru 457>,
    <&u2phy0>;
  phys = <&u2phy0_host>;
  phy-names = "usb";
  status = "disabled";
 };

 usb_host0_ohci: usb@fe3a0000 {
  compatible = "generic-ohci";
  reg = <0x0 0xfe3a0000 0x0 0x20000>;
  interrupts = <0 28 4 0>;
  clocks = <&cru 456>, <&cru 457>,
    <&u2phy0>;
  phys = <&u2phy0_host>;
  phy-names = "usb";
  status = "disabled";
 };

 usb_host1_ehci: usb@fe3c0000 {
  compatible = "generic-ehci";
  reg = <0x0 0xfe3c0000 0x0 0x20000>;
  interrupts = <0 30 4 0>;
  clocks = <&cru 458>, <&cru 459>,
    <&u2phy1>;
  phys = <&u2phy1_host>;
  phy-names = "usb";
  status = "disabled";
 };

 usb_host1_ohci: usb@fe3e0000 {
  compatible = "generic-ohci";
  reg = <0x0 0xfe3e0000 0x0 0x20000>;
  interrupts = <0 32 4 0>;
  clocks = <&cru 458>, <&cru 459>,
    <&u2phy1>;
  phys = <&u2phy1_host>;
  phy-names = "usb";
  status = "disabled";
 };
# 462 "arch/arm64/boot/dts/rockchip/rk3399.dtsi"
 usbdrd3_0: usb@fe800000 {
  compatible = "rockchip,rk3399-dwc3";
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;
  clocks = <&cru 129>, <&cru 131>,
    <&cru 246>, <&cru 248>,
    <&cru 244>, <&cru 249>;
  clock-names = "ref_clk", "suspend_clk",
         "bus_clk", "aclk_usb3_rksoc_axi_perf",
         "aclk_usb3", "grf_clk";
  resets = <&cru 293>;
  reset-names = "usb3-otg";
  status = "disabled";

  usbdrd_dwc3_0: usb@fe800000 {
   compatible = "snps,dwc3";
   reg = <0x0 0xfe800000 0x0 0x100000>;
   interrupts = <0 105 4 0>;
   clocks = <&cru 129>, <&cru 246>,
     <&cru 131>;
   clock-names = "ref", "bus_early", "suspend";
   dr_mode = "otg";
   phys = <&u2phy0_otg>, <&tcphy0_usb3>;
   phy-names = "usb2-phy", "usb3-phy";
   phy_type = "utmi_wide";
   snps,dis_enblslpm_quirk;
   snps,dis-u2-freeclk-exists-quirk;
   snps,dis_u2_susphy_quirk;
   snps,dis-del-phy-power-chg-quirk;
   snps,dis-tx-ipgap-linecheck-quirk;
   power-domains = <&power 24>;
   status = "disabled";
  };
 };

 usbdrd3_1: usb@fe900000 {
  compatible = "rockchip,rk3399-dwc3";
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;
  clocks = <&cru 130>, <&cru 132>,
    <&cru 247>, <&cru 248>,
    <&cru 244>, <&cru 249>;
  clock-names = "ref_clk", "suspend_clk",
         "bus_clk", "aclk_usb3_rksoc_axi_perf",
         "aclk_usb3", "grf_clk";
  resets = <&cru 294>;
  reset-names = "usb3-otg";
  status = "disabled";

  usbdrd_dwc3_1: usb@fe900000 {
   compatible = "snps,dwc3";
   reg = <0x0 0xfe900000 0x0 0x100000>;
   interrupts = <0 110 4 0>;
   clocks = <&cru 130>, <&cru 247>,
     <&cru 132>;
   clock-names = "ref", "bus_early", "suspend";
   dr_mode = "otg";
   phys = <&u2phy1_otg>, <&tcphy1_usb3>;
   phy-names = "usb2-phy", "usb3-phy";
   phy_type = "utmi_wide";
   snps,dis_enblslpm_quirk;
   snps,dis-u2-freeclk-exists-quirk;
   snps,dis_u2_susphy_quirk;
   snps,dis-del-phy-power-chg-quirk;
   snps,dis-tx-ipgap-linecheck-quirk;
   power-domains = <&power 24>;
   status = "disabled";
  };
 };

 cdn_dp: dp@fec00000 {
  compatible = "rockchip,rk3399-cdn-dp";
  reg = <0x0 0xfec00000 0x0 0x100000>;
  interrupts = <0 9 4 0>;
  assigned-clocks = <&cru 114>, <&cru 161>;
  assigned-clock-rates = <100000000>, <200000000>;
  clocks = <&cru 114>, <&cru 373>,
    <&cru 161>, <&cru 367>;
  clock-names = "core-clk", "pclk", "spdif", "grf";
  phys = <&tcphy0_dp>, <&tcphy1_dp>;
  power-domains = <&power 21>;
  resets = <&cru 259>, <&cru 328>,
    <&cru 330>, <&cru 253>;
  reset-names = "spdif", "dptx", "apb", "core";
  rockchip,grf = <&grf>;
  #sound-dai-cells = <1>;
  status = "disabled";

  ports {
   dp_in: port {
    #address-cells = <1>;
    #size-cells = <0>;

    dp_in_vopb: endpoint@0 {
     reg = <0>;
     remote-endpoint = <&vopb_out_dp>;
    };

    dp_in_vopl: endpoint@1 {
     reg = <1>;
     remote-endpoint = <&vopl_out_dp>;
    };
   };
  };
 };

 gic: interrupt-controller@fee00000 {
  compatible = "arm,gic-v3";
  #interrupt-cells = <4>;
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;
  interrupt-controller;

  reg = <0x0 0xfee00000 0 0x10000>,
        <0x0 0xfef00000 0 0xc0000>,
        <0x0 0xfff00000 0 0x10000>,
        <0x0 0xfff10000 0 0x10000>,
        <0x0 0xfff20000 0 0x10000>;
  interrupts = <1 9 4 0>;
  its: msi-controller@fee20000 {
   compatible = "arm,gic-v3-its";
   msi-controller;
   #msi-cells = <1>;
   reg = <0x0 0xfee20000 0x0 0x20000>;
  };

  ppi-partitions {
   ppi_cluster0: interrupt-partition-0 {
    affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
   };

   ppi_cluster1: interrupt-partition-1 {
    affinity = <&cpu_b0 &cpu_b1>;
   };
  };
 };

 saradc: saradc@ff100000 {
  compatible = "rockchip,rk3399-saradc";
  reg = <0x0 0xff100000 0x0 0x100>;
  interrupts = <0 62 4 0>;
  #io-channel-cells = <1>;
  clocks = <&cru 80>, <&cru 357>;
  clock-names = "saradc", "apb_pclk";
  resets = <&cru 212>;
  reset-names = "saradc-apb";
  status = "disabled";
 };

 crypto0: crypto@ff8b0000 {
  compatible = "rockchip,rk3399-crypto";
  reg = <0x0 0xff8b0000 0x0 0x4000>;
  interrupts = <0 0 4 0>;
  clocks = <&cru 464>, <&cru 466>, <&cru 133>;
  clock-names = "hclk_master", "hclk_slave", "sclk";
  resets = <&cru 181>, <&cru 174>, <&cru 175>;
  reset-names = "master", "slave", "crypto-rst";
 };

 crypto1: crypto@ff8b8000 {
  compatible = "rockchip,rk3399-crypto";
  reg = <0x0 0xff8b8000 0x0 0x4000>;
  interrupts = <0 135 4 0>;
  clocks = <&cru 465>, <&cru 467>, <&cru 134>;
  clock-names = "hclk_master", "hclk_slave", "sclk";
  resets = <&cru 186>, <&cru 184>, <&cru 185>;
  reset-names = "master", "slave", "crypto-rst";
 };

 i2c1: i2c@ff110000 {
  compatible = "rockchip,rk3399-i2c";
  reg = <0x0 0xff110000 0x0 0x1000>;
  assigned-clocks = <&cru 65>;
  assigned-clock-rates = <200000000>;
  clocks = <&cru 65>, <&cru 341>;
  clock-names = "i2c", "pclk";
  interrupts = <0 59 4 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c1_xfer>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c2: i2c@ff120000 {
  compatible = "rockchip,rk3399-i2c";
  reg = <0x0 0xff120000 0x0 0x1000>;
  assigned-clocks = <&cru 66>;
  assigned-clock-rates = <200000000>;
  clocks = <&cru 66>, <&cru 342>;
  clock-names = "i2c", "pclk";
  interrupts = <0 35 4 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c2_xfer>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c3: i2c@ff130000 {
  compatible = "rockchip,rk3399-i2c";
  reg = <0x0 0xff130000 0x0 0x1000>;
  assigned-clocks = <&cru 67>;
  assigned-clock-rates = <200000000>;
  clocks = <&cru 67>, <&cru 343>;
  clock-names = "i2c", "pclk";
  interrupts = <0 34 4 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c3_xfer>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c5: i2c@ff140000 {
  compatible = "rockchip,rk3399-i2c";
  reg = <0x0 0xff140000 0x0 0x1000>;
  assigned-clocks = <&cru 68>;
  assigned-clock-rates = <200000000>;
  clocks = <&cru 68>, <&cru 344>;
  clock-names = "i2c", "pclk";
  interrupts = <0 38 4 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c5_xfer>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c6: i2c@ff150000 {
  compatible = "rockchip,rk3399-i2c";
  reg = <0x0 0xff150000 0x0 0x1000>;
  assigned-clocks = <&cru 69>;
  assigned-clock-rates = <200000000>;
  clocks = <&cru 69>, <&cru 345>;
  clock-names = "i2c", "pclk";
  interrupts = <0 37 4 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c6_xfer>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c7: i2c@ff160000 {
  compatible = "rockchip,rk3399-i2c";
  reg = <0x0 0xff160000 0x0 0x1000>;
  assigned-clocks = <&cru 70>;
  assigned-clock-rates = <200000000>;
  clocks = <&cru 70>, <&cru 346>;
  clock-names = "i2c", "pclk";
  interrupts = <0 36 4 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c7_xfer>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 uart0: serial@ff180000 {
  compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
  reg = <0x0 0xff180000 0x0 0x100>;
  clocks = <&cru 81>, <&cru 352>;
  clock-names = "baudclk", "apb_pclk";
  interrupts = <0 99 4 0>;
  reg-shift = <2>;
  reg-io-width = <4>;
  pinctrl-names = "default";
  pinctrl-0 = <&uart0_xfer>;
  status = "disabled";
 };

 uart1: serial@ff190000 {
  compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
  reg = <0x0 0xff190000 0x0 0x100>;
  clocks = <&cru 82>, <&cru 353>;
  clock-names = "baudclk", "apb_pclk";
  interrupts = <0 98 4 0>;
  reg-shift = <2>;
  reg-io-width = <4>;
  pinctrl-names = "default";
  pinctrl-0 = <&uart1_xfer>;
  status = "disabled";
 };

 uart2: serial@ff1a0000 {
  compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
  reg = <0x0 0xff1a0000 0x0 0x100>;
  clocks = <&cru 83>, <&cru 354>;
  clock-names = "baudclk", "apb_pclk";
  interrupts = <0 100 4 0>;
  reg-shift = <2>;
  reg-io-width = <4>;
  pinctrl-names = "default";
  pinctrl-0 = <&uart2c_xfer>;
  status = "disabled";
 };

 uart3: serial@ff1b0000 {
  compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
  reg = <0x0 0xff1b0000 0x0 0x100>;
  clocks = <&cru 84>, <&cru 355>;
  clock-names = "baudclk", "apb_pclk";
  interrupts = <0 101 4 0>;
  reg-shift = <2>;
  reg-io-width = <4>;
  pinctrl-names = "default";
  pinctrl-0 = <&uart3_xfer>;
  status = "disabled";
 };

 spi0: spi@ff1c0000 {
  compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
  reg = <0x0 0xff1c0000 0x0 0x1000>;
  clocks = <&cru 71>, <&cru 347>;
  clock-names = "spiclk", "apb_pclk";
  interrupts = <0 68 4 0>;
  dmas = <&dmac_peri 10>, <&dmac_peri 11>;
  dma-names = "tx", "rx";
  pinctrl-names = "default";
  pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 spi1: spi@ff1d0000 {
  compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
  reg = <0x0 0xff1d0000 0x0 0x1000>;
  clocks = <&cru 72>, <&cru 348>;
  clock-names = "spiclk", "apb_pclk";
  interrupts = <0 53 4 0>;
  dmas = <&dmac_peri 12>, <&dmac_peri 13>;
  dma-names = "tx", "rx";
  pinctrl-names = "default";
  pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 spi2: spi@ff1e0000 {
  compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
  reg = <0x0 0xff1e0000 0x0 0x1000>;
  clocks = <&cru 73>, <&cru 349>;
  clock-names = "spiclk", "apb_pclk";
  interrupts = <0 52 4 0>;
  dmas = <&dmac_peri 14>, <&dmac_peri 15>;
  dma-names = "tx", "rx";
  pinctrl-names = "default";
  pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 spi4: spi@ff1f0000 {
  compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
  reg = <0x0 0xff1f0000 0x0 0x1000>;
  clocks = <&cru 74>, <&cru 350>;
  clock-names = "spiclk", "apb_pclk";
  interrupts = <0 67 4 0>;
  dmas = <&dmac_peri 18>, <&dmac_peri 19>;
  dma-names = "tx", "rx";
  pinctrl-names = "default";
  pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 spi5: spi@ff200000 {
  compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
  reg = <0x0 0xff200000 0x0 0x1000>;
  clocks = <&cru 75>, <&cru 351>;
  clock-names = "spiclk", "apb_pclk";
  interrupts = <0 132 4 0>;
  dmas = <&dmac_bus 8>, <&dmac_bus 9>;
  dma-names = "tx", "rx";
  pinctrl-names = "default";
  pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
  power-domains = <&power 28>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 thermal_zones: thermal-zones {
  cpu_thermal: cpu-thermal {
   polling-delay-passive = <100>;
   polling-delay = <1000>;

   thermal-sensors = <&tsadc 0>;

   trips {
    cpu_alert0: cpu_alert0 {
     temperature = <70000>;
     hysteresis = <2000>;
     type = "passive";
    };
    cpu_alert1: cpu_alert1 {
     temperature = <75000>;
     hysteresis = <2000>;
     type = "passive";
    };
    cpu_crit: cpu_crit {
     temperature = <95000>;
     hysteresis = <2000>;
     type = "critical";
    };
   };

   cooling-maps {
    map0 {
     trip = <&cpu_alert0>;
     cooling-device =
      <&cpu_b0 (~0) (~0)>,
      <&cpu_b1 (~0) (~0)>;
    };
    map1 {
     trip = <&cpu_alert1>;
     cooling-device =
      <&cpu_l0 (~0) (~0)>,
      <&cpu_l1 (~0) (~0)>,
      <&cpu_l2 (~0) (~0)>,
      <&cpu_l3 (~0) (~0)>,
      <&cpu_b0 (~0) (~0)>,
      <&cpu_b1 (~0) (~0)>;
    };
   };
  };

  gpu_thermal: gpu-thermal {
   polling-delay-passive = <100>;
   polling-delay = <1000>;

   thermal-sensors = <&tsadc 1>;

   trips {
    gpu_alert0: gpu_alert0 {
     temperature = <75000>;
     hysteresis = <2000>;
     type = "passive";
    };
    gpu_crit: gpu_crit {
     temperature = <95000>;
     hysteresis = <2000>;
     type = "critical";
    };
   };

   cooling-maps {
    map0 {
     trip = <&gpu_alert0>;
     cooling-device =
      <&gpu (~0) (~0)>;
    };
   };
  };
 };

 tsadc: tsadc@ff260000 {
  compatible = "rockchip,rk3399-tsadc";
  reg = <0x0 0xff260000 0x0 0x100>;
  interrupts = <0 97 4 0>;
  assigned-clocks = <&cru 79>;
  assigned-clock-rates = <750000>;
  clocks = <&cru 79>, <&cru 356>;
  clock-names = "tsadc", "apb_pclk";
  resets = <&cru 232>;
  reset-names = "tsadc-apb";
  rockchip,grf = <&grf>;
  rockchip,hw-tshut-temp = <95000>;
  pinctrl-names = "init", "default", "sleep";
  pinctrl-0 = <&otp_pin>;
  pinctrl-1 = <&otp_out>;
  pinctrl-2 = <&otp_pin>;
  #thermal-sensor-cells = <1>;
  status = "disabled";
 };

 qos_emmc: qos@ffa58000 {
  compatible = "rockchip,rk3399-qos", "syscon";
  reg = <0x0 0xffa58000 0x0 0x20>;
 };

 qos_gmac: qos@ffa5c000 {
  compatible = "rockchip,rk3399-qos", "syscon";
  reg = <0x0 0xffa5c000 0x0 0x20>;
 };

 qos_pcie: qos@ffa60080 {
  compatible = "rockchip,rk3399-qos", "syscon";
  reg = <0x0 0xffa60080 0x0 0x20>;
 };

 qos_usb_host0: qos@ffa60100 {
  compatible = "rockchip,rk3399-qos", "syscon";
  reg = <0x0 0xffa60100 0x0 0x20>;
 };

 qos_usb_host1: qos@ffa60180 {
  compatible = "rockchip,rk3399-qos", "syscon";
  reg = <0x0 0xffa60180 0x0 0x20>;
 };

 qos_usb_otg0: qos@ffa70000 {
  compatible = "rockchip,rk3399-qos", "syscon";
  reg = <0x0 0xffa70000 0x0 0x20>;
 };

 qos_usb_otg1: qos@ffa70080 {
  compatible = "rockchip,rk3399-qos", "syscon";
  reg = <0x0 0xffa70080 0x0 0x20>;
 };

 qos_sd: qos@ffa74000 {
  compatible = "rockchip,rk3399-qos", "syscon";
  reg = <0x0 0xffa74000 0x0 0x20>;
 };

 qos_sdioaudio: qos@ffa76000 {
  compatible = "rockchip,rk3399-qos", "syscon";
  reg = <0x0 0xffa76000 0x0 0x20>;
 };

 qos_hdcp: qos@ffa90000 {
  compatible = "rockchip,rk3399-qos", "syscon";
  reg = <0x0 0xffa90000 0x0 0x20>;
 };

 qos_iep: qos@ffa98000 {
  compatible = "rockchip,rk3399-qos", "syscon";
  reg = <0x0 0xffa98000 0x0 0x20>;
 };

 qos_isp0_m0: qos@ffaa0000 {
  compatible = "rockchip,rk3399-qos", "syscon";
  reg = <0x0 0xffaa0000 0x0 0x20>;
 };

 qos_isp0_m1: qos@ffaa0080 {
  compatible = "rockchip,rk3399-qos", "syscon";
  reg = <0x0 0xffaa0080 0x0 0x20>;
 };

 qos_isp1_m0: qos@ffaa8000 {
  compatible = "rockchip,rk3399-qos", "syscon";
  reg = <0x0 0xffaa8000 0x0 0x20>;
 };

 qos_isp1_m1: qos@ffaa8080 {
  compatible = "rockchip,rk3399-qos", "syscon";
  reg = <0x0 0xffaa8080 0x0 0x20>;
 };

 qos_rga_r: qos@ffab0000 {
  compatible = "rockchip,rk3399-qos", "syscon";
  reg = <0x0 0xffab0000 0x0 0x20>;
 };

 qos_rga_w: qos@ffab0080 {
  compatible = "rockchip,rk3399-qos", "syscon";
  reg = <0x0 0xffab0080 0x0 0x20>;
 };

 qos_video_m0: qos@ffab8000 {
  compatible = "rockchip,rk3399-qos", "syscon";
  reg = <0x0 0xffab8000 0x0 0x20>;
 };

 qos_video_m1_r: qos@ffac0000 {
  compatible = "rockchip,rk3399-qos", "syscon";
  reg = <0x0 0xffac0000 0x0 0x20>;
 };

 qos_video_m1_w: qos@ffac0080 {
  compatible = "rockchip,rk3399-qos", "syscon";
  reg = <0x0 0xffac0080 0x0 0x20>;
 };

 qos_vop_big_r: qos@ffac8000 {
  compatible = "rockchip,rk3399-qos", "syscon";
  reg = <0x0 0xffac8000 0x0 0x20>;
 };

 qos_vop_big_w: qos@ffac8080 {
  compatible = "rockchip,rk3399-qos", "syscon";
  reg = <0x0 0xffac8080 0x0 0x20>;
 };

 qos_vop_little: qos@ffad0000 {
  compatible = "rockchip,rk3399-qos", "syscon";
  reg = <0x0 0xffad0000 0x0 0x20>;
 };

 qos_perihp: qos@ffad8080 {
  compatible = "rockchip,rk3399-qos", "syscon";
  reg = <0x0 0xffad8080 0x0 0x20>;
 };

 qos_gpu: qos@ffae0000 {
  compatible = "rockchip,rk3399-qos", "syscon";
  reg = <0x0 0xffae0000 0x0 0x20>;
 };

 pmu: power-management@ff310000 {
  compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
  reg = <0x0 0xff310000 0x0 0x1000>;
# 1082 "arch/arm64/boot/dts/rockchip/rk3399.dtsi"
  power: power-controller {
   compatible = "rockchip,rk3399-power-controller";
   #power-domain-cells = <1>;
   #address-cells = <1>;
   #size-cells = <0>;


   power-domain@34 {
    reg = <34>;
    clocks = <&cru 225>,
      <&cru 477>;
    pm_qos = <&qos_iep>;
    #power-domain-cells = <0>;
   };
   power-domain@33 {
    reg = <33>;
    clocks = <&cru 220>,
      <&cru 485>;
    pm_qos = <&qos_rga_r>,
      <&qos_rga_w>;
    #power-domain-cells = <0>;
   };
   power-domain@31 {
    reg = <31>;
    clocks = <&cru 235>,
      <&cru 490>;
    pm_qos = <&qos_video_m0>;
    #power-domain-cells = <0>;
   };
   power-domain@32 {
    reg = <32>;
    clocks = <&cru 237>,
      <&cru 492>;
    pm_qos = <&qos_video_m1_r>,
      <&qos_video_m1_w>;
    #power-domain-cells = <0>;
   };


   power-domain@35 {
    reg = <35>;
    clocks = <&cru 208>;
    pm_qos = <&qos_gpu>;
    #power-domain-cells = <0>;
   };


   power-domain@25 {
    reg = <25>;
    clocks = <&cru 364>;
    #power-domain-cells = <0>;
   };
   power-domain@23 {
    reg = <23>;
    clocks = <&cru 240>;
    pm_qos = <&qos_emmc>;
    #power-domain-cells = <0>;
   };
   power-domain@22 {
    reg = <22>;
    clocks = <&cru 213>,
      <&cru 358>;
    pm_qos = <&qos_gmac>;
    #power-domain-cells = <0>;
   };
   power-domain@27 {
    reg = <27>;
    clocks = <&cru 462>,
      <&cru 76>;
    pm_qos = <&qos_sd>;
    #power-domain-cells = <0>;
   };
   power-domain@28 {
    reg = <28>;
    clocks = <&cru 494>;
    pm_qos = <&qos_sdioaudio>;
    #power-domain-cells = <0>;
   };
   power-domain@8 {
    reg = <8>;
    clocks = <&cru 126>,
      <&cru 125>;
    #power-domain-cells = <0>;
   };
   power-domain@9 {
    reg = <9>;
    clocks = <&cru 128>,
      <&cru 127>;
    #power-domain-cells = <0>;
   };
   power-domain@24 {
    reg = <24>;
    clocks = <&cru 244>;
    pm_qos = <&qos_usb_otg0>,
      <&qos_usb_otg1>;
    #power-domain-cells = <0>;
   };
   power-domain@15 {
    reg = <15>;
    #power-domain-cells = <1>;
    #address-cells = <1>;
    #size-cells = <0>;

    power-domain@21 {
     reg = <21>;
     clocks = <&cru 222>,
       <&cru 487>,
       <&cru 370>;
     pm_qos = <&qos_hdcp>;
     #power-domain-cells = <0>;
    };
    power-domain@19 {
     reg = <19>;
     clocks = <&cru 229>,
       <&cru 479>;
     pm_qos = <&qos_isp0_m0>,
       <&qos_isp0_m1>;
     #power-domain-cells = <0>;
    };
    power-domain@20 {
     reg = <20>;
     clocks = <&cru 230>,
       <&cru 480>;
     pm_qos = <&qos_isp1_m0>,
       <&qos_isp1_m1>;
     #power-domain-cells = <0>;
    };
    power-domain@16 {
     reg = <16>;
     #power-domain-cells = <1>;
     #address-cells = <1>;
     #size-cells = <0>;

     power-domain@17 {
      reg = <17>;
      clocks = <&cru 217>,
        <&cru 473>;
      pm_qos = <&qos_vop_big_r>,
        <&qos_vop_big_w>;
      #power-domain-cells = <0>;
     };
     power-domain@18 {
      reg = <18>;
      clocks = <&cru 219>,
        <&cru 475>;
      pm_qos = <&qos_vop_little>;
      #power-domain-cells = <0>;
     };
    };
   };
  };
 };

 pmugrf: syscon@ff320000 {
  compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
  reg = <0x0 0xff320000 0x0 0x1000>;

  pmu_io_domains: io-domains {
   compatible = "rockchip,rk3399-pmu-io-voltage-domain";
   status = "disabled";
  };

  reboot-mode {
   compatible = "syscon-reboot-mode";
   offset = <0x300>;
   mode-normal = <0>;
   mode-maskrom = <0xef08a53c>;
  };
 };

 spi3: spi@ff350000 {
  compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
  reg = <0x0 0xff350000 0x0 0x1000>;
  clocks = <&pmucru 3>, <&pmucru 31>;
  clock-names = "spiclk", "apb_pclk";
  interrupts = <0 60 4 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 uart4: serial@ff370000 {
  compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
  reg = <0x0 0xff370000 0x0 0x100>;
  clocks = <&pmucru 6>, <&pmucru 34>;
  clock-names = "baudclk", "apb_pclk";
  interrupts = <0 102 4 0>;
  reg-shift = <2>;
  reg-io-width = <4>;
  pinctrl-names = "default";
  pinctrl-0 = <&uart4_xfer>;
  status = "disabled";
 };

 i2c0: i2c@ff3c0000 {
  compatible = "rockchip,rk3399-i2c";
  reg = <0x0 0xff3c0000 0x0 0x1000>;
  assigned-clocks = <&pmucru 9>;
  assigned-clock-rates = <200000000>;
  clocks = <&pmucru 9>, <&pmucru 27>;
  clock-names = "i2c", "pclk";
  interrupts = <0 57 4 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c0_xfer>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c4: i2c@ff3d0000 {
  compatible = "rockchip,rk3399-i2c";
  reg = <0x0 0xff3d0000 0x0 0x1000>;
  assigned-clocks = <&pmucru 10>;
  assigned-clock-rates = <200000000>;
  clocks = <&pmucru 10>, <&pmucru 28>;
  clock-names = "i2c", "pclk";
  interrupts = <0 56 4 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c4_xfer>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c8: i2c@ff3e0000 {
  compatible = "rockchip,rk3399-i2c";
  reg = <0x0 0xff3e0000 0x0 0x1000>;
  assigned-clocks = <&pmucru 11>;
  assigned-clock-rates = <200000000>;
  clocks = <&pmucru 11>, <&pmucru 29>;
  clock-names = "i2c", "pclk";
  interrupts = <0 58 4 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c8_xfer>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 pwm0: pwm@ff420000 {
  compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
  reg = <0x0 0xff420000 0x0 0x10>;
  #pwm-cells = <3>;
  pinctrl-names = "default";
  pinctrl-0 = <&pwm0_pin>;
  clocks = <&pmucru 30>;
  status = "disabled";
 };

 pwm1: pwm@ff420010 {
  compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
  reg = <0x0 0xff420010 0x0 0x10>;
  #pwm-cells = <3>;
  pinctrl-names = "default";
  pinctrl-0 = <&pwm1_pin>;
  clocks = <&pmucru 30>;
  status = "disabled";
 };

 pwm2: pwm@ff420020 {
  compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
  reg = <0x0 0xff420020 0x0 0x10>;
  #pwm-cells = <3>;
  pinctrl-names = "default";
  pinctrl-0 = <&pwm2_pin>;
  clocks = <&pmucru 30>;
  status = "disabled";
 };

 pwm3: pwm@ff420030 {
  compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
  reg = <0x0 0xff420030 0x0 0x10>;
  #pwm-cells = <3>;
  pinctrl-names = "default";
  pinctrl-0 = <&pwm3a_pin>;
  clocks = <&pmucru 30>;
  status = "disabled";
 };

 dfi: dfi@ff630000 {
  reg = <0x00 0xff630000 0x00 0x4000>;
  compatible = "rockchip,rk3399-dfi";
  rockchip,pmu = <&pmugrf>;
  interrupts = <0 131 4 0>;
  clocks = <&cru 377>;
  clock-names = "pclk_ddr_mon";
  status = "disabled";
 };

 vpu: video-codec@ff650000 {
  compatible = "rockchip,rk3399-vpu";
  reg = <0x0 0xff650000 0x0 0x800>;
  interrupts = <0 114 4 0>,
        <0 113 4 0>;
  interrupt-names = "vepu", "vdpu";
  clocks = <&cru 235>, <&cru 490>;
  clock-names = "aclk", "hclk";
  iommus = <&vpu_mmu>;
  power-domains = <&power 31>;
 };

 vpu_mmu: iommu@ff650800 {
  compatible = "rockchip,iommu";
  reg = <0x0 0xff650800 0x0 0x40>;
  interrupts = <0 115 4 0>;
  clocks = <&cru 235>, <&cru 490>;
  clock-names = "aclk", "iface";
  #iommu-cells = <0>;
  power-domains = <&power 31>;
 };

 vdec: video-codec@ff660000 {
  compatible = "rockchip,rk3399-vdec";
  reg = <0x0 0xff660000 0x0 0x400>;
  interrupts = <0 116 4 0>;
  clocks = <&cru 237>, <&cru 492>,
    <&cru 159>, <&cru 158>;
  clock-names = "axi", "ahb", "cabac", "core";
  iommus = <&vdec_mmu>;
  power-domains = <&power 32>;
 };

 vdec_mmu: iommu@ff660480 {
  compatible = "rockchip,iommu";
  reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
  interrupts = <0 117 4 0>;
  clocks = <&cru 237>, <&cru 492>;
  clock-names = "aclk", "iface";
  power-domains = <&power 32>;
  #iommu-cells = <0>;
 };

 iep_mmu: iommu@ff670800 {
  compatible = "rockchip,iommu";
  reg = <0x0 0xff670800 0x0 0x40>;
  interrupts = <0 42 4 0>;
  clocks = <&cru 225>, <&cru 477>;
  clock-names = "aclk", "iface";
  #iommu-cells = <0>;
  status = "disabled";
 };

 rga: rga@ff680000 {
  compatible = "rockchip,rk3399-rga";
  reg = <0x0 0xff680000 0x0 0x10000>;
  interrupts = <0 55 4 0>;
  clocks = <&cru 220>, <&cru 485>, <&cru 109>;
  clock-names = "aclk", "hclk", "sclk";
  resets = <&cru 106>, <&cru 103>, <&cru 105>;
  reset-names = "core", "axi", "ahb";
  power-domains = <&power 33>;
 };

 efuse0: efuse@ff690000 {
  compatible = "rockchip,rk3399-efuse";
  reg = <0x0 0xff690000 0x0 0x80>;
  #address-cells = <1>;
  #size-cells = <1>;
  clocks = <&cru 381>;
  clock-names = "pclk_efuse";


  cpu_id: cpu-id@7 {
   reg = <0x07 0x10>;
  };
  cpub_leakage: cpu-leakage@17 {
   reg = <0x17 0x1>;
  };
  gpu_leakage: gpu-leakage@18 {
   reg = <0x18 0x1>;
  };
  center_leakage: center-leakage@19 {
   reg = <0x19 0x1>;
  };
  cpul_leakage: cpu-leakage@1a {
   reg = <0x1a 0x1>;
  };
  logic_leakage: logic-leakage@1b {
   reg = <0x1b 0x1>;
  };
  wafer_info: wafer-info@1c {
   reg = <0x1c 0x1>;
  };
 };

 dmac_bus: dma-controller@ff6d0000 {
  compatible = "arm,pl330", "arm,primecell";
  reg = <0x0 0xff6d0000 0x0 0x4000>;
  interrupts = <0 5 4 0>,
        <0 6 4 0>;
  #dma-cells = <1>;
  arm,pl330-periph-burst;
  clocks = <&cru 211>;
  clock-names = "apb_pclk";
 };

 dmac_peri: dma-controller@ff6e0000 {
  compatible = "arm,pl330", "arm,primecell";
  reg = <0x0 0xff6e0000 0x0 0x4000>;
  interrupts = <0 7 4 0>,
        <0 8 4 0>;
  #dma-cells = <1>;
  arm,pl330-periph-burst;
  clocks = <&cru 212>;
  clock-names = "apb_pclk";
 };

 pmucru: clock-controller@ff750000 {
  compatible = "rockchip,rk3399-pmucru";
  reg = <0x0 0xff750000 0x0 0x1000>;
  clocks = <&xin24m>;
  clock-names = "xin24m";
  rockchip,grf = <&pmugrf>;
  #clock-cells = <1>;
  #reset-cells = <1>;
  assigned-clocks = <&pmucru 1>;
  assigned-clock-rates = <676000000>;
 };

 cru: clock-controller@ff760000 {
  compatible = "rockchip,rk3399-cru";
  reg = <0x0 0xff760000 0x0 0x1000>;
  clocks = <&xin24m>;
  clock-names = "xin24m";
  rockchip,grf = <&grf>;
  #clock-cells = <1>;
  #reset-cells = <1>;
  assigned-clocks =
   <&cru 5>, <&cru 4>,
   <&cru 6>,
   <&cru 192>, <&cru 448>,
   <&cru 320>,
   <&cru 194>, <&cru 449>,
   <&cru 322>, <&cru 201>,
   <&cru 450>, <&cru 323>,
   <&cru 227>, <&cru 222>,
   <&cru 262>,
   <&cru 376>,
   <&cru 237>;
  assigned-clock-rates =
    <594000000>, <800000000>,
   <1000000000>,
    <150000000>, <75000000>,
     <37500000>,
    <100000000>, <100000000>,
     <50000000>, <600000000>,
    <100000000>, <50000000>,
    <400000000>, <400000000>,
    <200000000>,
    <200000000>,
    <400000000>;
 };

 grf: syscon@ff770000 {
  compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
  reg = <0x0 0xff770000 0x0 0x10000>;
  #address-cells = <1>;
  #size-cells = <1>;

  io_domains: io-domains {
   compatible = "rockchip,rk3399-io-voltage-domain";
   status = "disabled";
  };

  mipi_dphy_rx0: mipi-dphy-rx0 {
   compatible = "rockchip,rk3399-mipi-dphy-rx0";
   clocks = <&cru 119>,
     <&cru 165>,
     <&cru 367>;
   clock-names = "dphy-ref", "dphy-cfg", "grf";
   power-domains = <&power 15>;
   #phy-cells = <0>;
   status = "disabled";
  };

  u2phy0: usb2phy@e450 {
   compatible = "rockchip,rk3399-usb2phy";
   reg = <0xe450 0x10>;
   clocks = <&cru 123>;
   clock-names = "phyclk";
   #clock-cells = <0>;
   clock-output-names = "clk_usbphy0_480m";
   status = "disabled";

   u2phy0_host: host-port {
    #phy-cells = <0>;
    interrupts = <0 27 4 0>;
    interrupt-names = "linestate";
    status = "disabled";
   };

   u2phy0_otg: otg-port {
    #phy-cells = <0>;
    interrupts = <0 103 4 0>,
          <0 104 4 0>,
          <0 106 4 0>;
    interrupt-names = "otg-bvalid", "otg-id",
        "linestate";
    status = "disabled";
   };
  };

  u2phy1: usb2phy@e460 {
   compatible = "rockchip,rk3399-usb2phy";
   reg = <0xe460 0x10>;
   clocks = <&cru 124>;
   clock-names = "phyclk";
   #clock-cells = <0>;
   clock-output-names = "clk_usbphy1_480m";
   status = "disabled";

   u2phy1_host: host-port {
    #phy-cells = <0>;
    interrupts = <0 31 4 0>;
    interrupt-names = "linestate";
    status = "disabled";
   };

   u2phy1_otg: otg-port {
    #phy-cells = <0>;
    interrupts = <0 108 4 0>,
          <0 109 4 0>,
          <0 111 4 0>;
    interrupt-names = "otg-bvalid", "otg-id",
        "linestate";
    status = "disabled";
   };
  };

  emmc_phy: phy@f780 {
   compatible = "rockchip,rk3399-emmc-phy";
   reg = <0xf780 0x24>;
   clocks = <&sdhci>;
   clock-names = "emmcclk";
   drive-impedance-ohm = <50>;
   #phy-cells = <0>;
   status = "disabled";
  };

  pcie_phy: pcie-phy {
   compatible = "rockchip,rk3399-pcie-phy";
   clocks = <&cru 138>;
   clock-names = "refclk";
   #phy-cells = <1>;
   resets = <&cru 135>;
   reset-names = "phy";
   status = "disabled";
  };
 };

 tcphy0: phy@ff7c0000 {
  compatible = "rockchip,rk3399-typec-phy";
  reg = <0x0 0xff7c0000 0x0 0x40000>;
  clocks = <&cru 126>,
    <&cru 125>;
  clock-names = "tcpdcore", "tcpdphy-ref";
  assigned-clocks = <&cru 126>;
  assigned-clock-rates = <50000000>;
  power-domains = <&power 8>;
  resets = <&cru 149>,
    <&cru 148>,
    <&cru 332>;
  reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
  rockchip,grf = <&grf>;
  status = "disabled";

  tcphy0_dp: dp-port {
   #phy-cells = <0>;
  };

  tcphy0_usb3: usb3-port {
   #phy-cells = <0>;
  };
 };

 tcphy1: phy@ff800000 {
  compatible = "rockchip,rk3399-typec-phy";
  reg = <0x0 0xff800000 0x0 0x40000>;
  clocks = <&cru 128>,
    <&cru 127>;
  clock-names = "tcpdcore", "tcpdphy-ref";
  assigned-clocks = <&cru 128>;
  assigned-clock-rates = <50000000>;
  power-domains = <&power 9>;
  resets = <&cru 157>,
    <&cru 156>,
    <&cru 333>;
  reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
  rockchip,grf = <&grf>;
  status = "disabled";

  tcphy1_dp: dp-port {
   #phy-cells = <0>;
  };

  tcphy1_usb3: usb3-port {
   #phy-cells = <0>;
  };
 };

 watchdog@ff848000 {
  compatible = "rockchip,rk3399-wdt", "snps,dw-wdt";
  reg = <0x0 0xff848000 0x0 0x100>;
  clocks = <&cru 380>;
  interrupts = <0 120 4 0>;
 };

 rktimer: rktimer@ff850000 {
  compatible = "rockchip,rk3399-timer";
  reg = <0x0 0xff850000 0x0 0x1000>;
  interrupts = <0 81 4 0>;
  clocks = <&cru 360>, <&cru 90>;
  clock-names = "pclk", "timer";
 };

 spdif: spdif@ff870000 {
  compatible = "rockchip,rk3399-spdif";
  reg = <0x0 0xff870000 0x0 0x1000>;
  interrupts = <0 66 4 0>;
  dmas = <&dmac_bus 7>;
  dma-names = "tx";
  clock-names = "mclk", "hclk";
  clocks = <&cru 85>, <&cru 471>;
  pinctrl-names = "default";
  pinctrl-0 = <&spdif_bus>;
  power-domains = <&power 28>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 i2s0: i2s@ff880000 {
  compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
  reg = <0x0 0xff880000 0x0 0x1000>;
  rockchip,grf = <&grf>;
  interrupts = <0 39 4 0>;
  dmas = <&dmac_bus 0>, <&dmac_bus 1>;
  dma-names = "tx", "rx";
  clock-names = "i2s_clk", "i2s_hclk";
  clocks = <&cru 86>, <&cru 468>;
  pinctrl-names = "bclk_on", "bclk_off";
  pinctrl-0 = <&i2s0_8ch_bus>;
  pinctrl-1 = <&i2s0_8ch_bus_bclk_off>;
  power-domains = <&power 28>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 i2s1: i2s@ff890000 {
  compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
  reg = <0x0 0xff890000 0x0 0x1000>;
  interrupts = <0 40 4 0>;
  dmas = <&dmac_bus 2>, <&dmac_bus 3>;
  dma-names = "tx", "rx";
  clock-names = "i2s_clk", "i2s_hclk";
  clocks = <&cru 87>, <&cru 469>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2s1_2ch_bus>;
  power-domains = <&power 28>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 i2s2: i2s@ff8a0000 {
  compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
  reg = <0x0 0xff8a0000 0x0 0x1000>;
  interrupts = <0 41 4 0>;
  dmas = <&dmac_bus 4>, <&dmac_bus 5>;
  dma-names = "tx", "rx";
  clock-names = "i2s_clk", "i2s_hclk";
  clocks = <&cru 88>, <&cru 470>;
  power-domains = <&power 28>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 vopl: vop@ff8f0000 {
  compatible = "rockchip,rk3399-vop-lit";
  reg = <0x0 0xff8f0000 0x0 0x2000>, <0x0 0xff8f2000 0x0 0x400>;
  interrupts = <0 119 4 0>;
  assigned-clocks = <&cru 219>, <&cru 475>;
  assigned-clock-rates = <400000000>, <100000000>;
  clocks = <&cru 219>, <&cru 181>, <&cru 475>;
  clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
  iommus = <&vopl_mmu>;
  power-domains = <&power 18>;
  resets = <&cru 275>, <&cru 279>, <&cru 281>;
  reset-names = "axi", "ahb", "dclk";
  status = "disabled";

  vopl_out: port {
   #address-cells = <1>;
   #size-cells = <0>;

   vopl_out_mipi: endpoint@0 {
    reg = <0>;
    remote-endpoint = <&mipi_in_vopl>;
   };

   vopl_out_edp: endpoint@1 {
    reg = <1>;
    remote-endpoint = <&edp_in_vopl>;
   };

   vopl_out_hdmi: endpoint@2 {
    reg = <2>;
    remote-endpoint = <&hdmi_in_vopl>;
   };

   vopl_out_mipi1: endpoint@3 {
    reg = <3>;
    remote-endpoint = <&mipi1_in_vopl>;
   };

   vopl_out_dp: endpoint@4 {
    reg = <4>;
    remote-endpoint = <&dp_in_vopl>;
   };
  };
 };

 vopl_mmu: iommu@ff8f3f00 {
  compatible = "rockchip,iommu";
  reg = <0x0 0xff8f3f00 0x0 0x100>;
  interrupts = <0 119 4 0>;
  clocks = <&cru 219>, <&cru 475>;
  clock-names = "aclk", "iface";
  power-domains = <&power 18>;
  #iommu-cells = <0>;
  status = "disabled";
 };

 vopb: vop@ff900000 {
  compatible = "rockchip,rk3399-vop-big";
  reg = <0x0 0xff900000 0x0 0x2000>, <0x0 0xff902000 0x0 0x1000>;
  interrupts = <0 118 4 0>;
  assigned-clocks = <&cru 217>, <&cru 473>;
  assigned-clock-rates = <400000000>, <100000000>;
  clocks = <&cru 217>, <&cru 180>, <&cru 473>;
  clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
  iommus = <&vopb_mmu>;
  power-domains = <&power 17>;
  resets = <&cru 274>, <&cru 278>, <&cru 280>;
  reset-names = "axi", "ahb", "dclk";
  status = "disabled";

  vopb_out: port {
   #address-cells = <1>;
   #size-cells = <0>;

   vopb_out_edp: endpoint@0 {
    reg = <0>;
    remote-endpoint = <&edp_in_vopb>;
   };

   vopb_out_mipi: endpoint@1 {
    reg = <1>;
    remote-endpoint = <&mipi_in_vopb>;
   };

   vopb_out_hdmi: endpoint@2 {
    reg = <2>;
    remote-endpoint = <&hdmi_in_vopb>;
   };

   vopb_out_mipi1: endpoint@3 {
    reg = <3>;
    remote-endpoint = <&mipi1_in_vopb>;
   };

   vopb_out_dp: endpoint@4 {
    reg = <4>;
    remote-endpoint = <&dp_in_vopb>;
   };
  };
 };

 vopb_mmu: iommu@ff903f00 {
  compatible = "rockchip,iommu";
  reg = <0x0 0xff903f00 0x0 0x100>;
  interrupts = <0 118 4 0>;
  clocks = <&cru 217>, <&cru 473>;
  clock-names = "aclk", "iface";
  power-domains = <&power 17>;
  #iommu-cells = <0>;
  status = "disabled";
 };

 isp0: isp0@ff910000 {
  compatible = "rockchip,rk3399-cif-isp";
  reg = <0x0 0xff910000 0x0 0x4000>;
  interrupts = <0 43 4 0>;
  clocks = <&cru 110>,
    <&cru 233>,
    <&cru 483>;
  clock-names = "isp", "aclk", "hclk";
  iommus = <&isp0_mmu>;
  phys = <&mipi_dphy_rx0>;
  phy-names = "dphy";
  power-domains = <&power 19>;
  status = "disabled";

  ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    #address-cells = <1>;
    #size-cells = <0>;
   };
  };
 };

 isp0_mmu: iommu@ff914000 {
  compatible = "rockchip,iommu";
  reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
  interrupts = <0 43 4 0>;
  clocks = <&cru 233>, <&cru 483>;
  clock-names = "aclk", "iface";
  #iommu-cells = <0>;
  power-domains = <&power 19>;
  rockchip,disable-mmu-reset;
 };

 isp1: isp1@ff920000 {
  compatible = "rockchip,rk3399-cif-isp";
  reg = <0x0 0xff920000 0x0 0x4000>;
  interrupts = <0 44 4 0>;
  clocks = <&cru 111>,
    <&cru 234>,
    <&cru 484>;
  clock-names = "isp", "aclk", "hclk";
  iommus = <&isp1_mmu>;
  phys = <&mipi_dsi1>;
  phy-names = "dphy";
  power-domains = <&power 20>;
  status = "disabled";

  ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    #address-cells = <1>;
    #size-cells = <0>;
   };
  };
 };

 isp1_mmu: iommu@ff924000 {
  compatible = "rockchip,iommu";
  reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
  interrupts = <0 44 4 0>;
  clocks = <&cru 234>, <&cru 484>;
  clock-names = "aclk", "iface";
  #iommu-cells = <0>;
  power-domains = <&power 20>;
  rockchip,disable-mmu-reset;
 };

 hdmi_sound: hdmi-sound {
  compatible = "simple-audio-card";
  simple-audio-card,format = "i2s";
  simple-audio-card,mclk-fs = <256>;
  simple-audio-card,name = "hdmi-sound";
  status = "disabled";

  simple-audio-card,cpu {
   sound-dai = <&i2s2>;
  };
  simple-audio-card,codec {
   sound-dai = <&hdmi>;
  };
 };

 hdmi: hdmi@ff940000 {
  compatible = "rockchip,rk3399-dw-hdmi";
  reg = <0x0 0xff940000 0x0 0x20000>;
  interrupts = <0 23 4 0>;
  clocks = <&cru 372>,
    <&cru 113>,
    <&cru 112>,
    <&cru 367>,
    <&cru 7>;
  clock-names = "iahb", "isfr", "cec", "grf", "ref";
  power-domains = <&power 21>;
  reg-io-width = <4>;
  rockchip,grf = <&grf>;
  #sound-dai-cells = <0>;
  status = "disabled";

  ports {
   hdmi_in: port {
    #address-cells = <1>;
    #size-cells = <0>;

    hdmi_in_vopb: endpoint@0 {
     reg = <0>;
     remote-endpoint = <&vopb_out_hdmi>;
    };
    hdmi_in_vopl: endpoint@1 {
     reg = <1>;
     remote-endpoint = <&vopl_out_hdmi>;
    };
   };
  };
 };

 mipi_dsi: dsi@ff960000 {
  compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
  reg = <0x0 0xff960000 0x0 0x8000>;
  interrupts = <0 45 4 0>;
  clocks = <&cru 162>, <&cru 368>,
    <&cru 163>, <&cru 367>;
  clock-names = "ref", "pclk", "phy_cfg", "grf";
  power-domains = <&power 15>;
  resets = <&cru 251>;
  reset-names = "apb";
  rockchip,grf = <&grf>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";

  ports {
   #address-cells = <1>;
   #size-cells = <0>;

   mipi_in: port@0 {
    reg = <0>;
    #address-cells = <1>;
    #size-cells = <0>;

    mipi_in_vopb: endpoint@0 {
     reg = <0>;
     remote-endpoint = <&vopb_out_mipi>;
    };

    mipi_in_vopl: endpoint@1 {
     reg = <1>;
     remote-endpoint = <&vopl_out_mipi>;
    };
   };

   mipi_out: port@1 {
    reg = <1>;
   };
  };
 };

 mipi_dsi1: dsi@ff968000 {
  compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
  reg = <0x0 0xff968000 0x0 0x8000>;
  interrupts = <0 46 4 0>;
  clocks = <&cru 162>, <&cru 369>,
    <&cru 164>, <&cru 367>;
  clock-names = "ref", "pclk", "phy_cfg", "grf";
  power-domains = <&power 15>;
  resets = <&cru 252>;
  reset-names = "apb";
  rockchip,grf = <&grf>;
  #address-cells = <1>;
  #size-cells = <0>;
  #phy-cells = <0>;
  status = "disabled";

  ports {
   #address-cells = <1>;
   #size-cells = <0>;

   mipi1_in: port@0 {
    reg = <0>;
    #address-cells = <1>;
    #size-cells = <0>;

    mipi1_in_vopb: endpoint@0 {
     reg = <0>;
     remote-endpoint = <&vopb_out_mipi1>;
    };

    mipi1_in_vopl: endpoint@1 {
     reg = <1>;
     remote-endpoint = <&vopl_out_mipi1>;
    };
   };

   mipi1_out: port@1 {
    reg = <1>;
   };
  };
 };

 edp: dp@ff970000 {
  compatible = "rockchip,rk3399-edp";
  reg = <0x0 0xff970000 0x0 0x8000>;
  interrupts = <0 10 4 0>;
  clocks = <&cru 362>, <&cru 364>, <&cru 367>;
  clock-names = "dp", "pclk", "grf";
  pinctrl-names = "default";
  pinctrl-0 = <&edp_hpd>;
  power-domains = <&power 25>;
  resets = <&cru 285>;
  reset-names = "dp";
  rockchip,grf = <&grf>;
  status = "disabled";

  ports {
   #address-cells = <1>;
   #size-cells = <0>;

   edp_in: port@0 {
    reg = <0>;
    #address-cells = <1>;
    #size-cells = <0>;

    edp_in_vopb: endpoint@0 {
     reg = <0>;
     remote-endpoint = <&vopb_out_edp>;
    };

    edp_in_vopl: endpoint@1 {
     reg = <1>;
     remote-endpoint = <&vopl_out_edp>;
    };
   };

   edp_out: port@1 {
    reg = <1>;
   };
  };
 };

 gpu: gpu@ff9a0000 {
  compatible = "rockchip,rk3399-mali", "arm,mali-t860";
  reg = <0x0 0xff9a0000 0x0 0x10000>;
  interrupts = <0 20 4 0>,
        <0 21 4 0>,
        <0 19 4 0>;
  interrupt-names = "job", "mmu", "gpu";
  clocks = <&cru 208>;
  #cooling-cells = <2>;
  power-domains = <&power 35>;
  status = "disabled";
 };

 pinctrl: pinctrl {
  compatible = "rockchip,rk3399-pinctrl";
  rockchip,grf = <&grf>;
  rockchip,pmu = <&pmugrf>;
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;

  gpio0: gpio@ff720000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xff720000 0x0 0x100>;
   clocks = <&pmucru 23>;
   interrupts = <0 14 4 0>;

   gpio-controller;
   #gpio-cells = <0x2>;

   interrupt-controller;
   #interrupt-cells = <0x2>;
  };

  gpio1: gpio@ff730000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xff730000 0x0 0x100>;
   clocks = <&pmucru 24>;
   interrupts = <0 15 4 0>;

   gpio-controller;
   #gpio-cells = <0x2>;

   interrupt-controller;
   #interrupt-cells = <0x2>;
  };

  gpio2: gpio@ff780000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xff780000 0x0 0x100>;
   clocks = <&cru 336>;
   interrupts = <0 16 4 0>;

   gpio-controller;
   #gpio-cells = <0x2>;

   interrupt-controller;
   #interrupt-cells = <0x2>;
  };

  gpio3: gpio@ff788000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xff788000 0x0 0x100>;
   clocks = <&cru 337>;
   interrupts = <0 17 4 0>;

   gpio-controller;
   #gpio-cells = <0x2>;

   interrupt-controller;
   #interrupt-cells = <0x2>;
  };

  gpio4: gpio@ff790000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xff790000 0x0 0x100>;
   clocks = <&cru 338>;
   interrupts = <0 18 4 0>;

   gpio-controller;
   #gpio-cells = <0x2>;

   interrupt-controller;
   #interrupt-cells = <0x2>;
  };

  pcfg_pull_up: pcfg-pull-up {
   bias-pull-up;
  };

  pcfg_pull_down: pcfg-pull-down {
   bias-pull-down;
  };

  pcfg_pull_none: pcfg-pull-none {
   bias-disable;
  };

  pcfg_pull_none_12ma: pcfg-pull-none-12ma {
   bias-disable;
   drive-strength = <12>;
  };

  pcfg_pull_none_13ma: pcfg-pull-none-13ma {
   bias-disable;
   drive-strength = <13>;
  };

  pcfg_pull_none_18ma: pcfg-pull-none-18ma {
   bias-disable;
   drive-strength = <18>;
  };

  pcfg_pull_none_20ma: pcfg-pull-none-20ma {
   bias-disable;
   drive-strength = <20>;
  };

  pcfg_pull_up_2ma: pcfg-pull-up-2ma {
   bias-pull-up;
   drive-strength = <2>;
  };

  pcfg_pull_up_8ma: pcfg-pull-up-8ma {
   bias-pull-up;
   drive-strength = <8>;
  };

  pcfg_pull_up_18ma: pcfg-pull-up-18ma {
   bias-pull-up;
   drive-strength = <18>;
  };

  pcfg_pull_up_20ma: pcfg-pull-up-20ma {
   bias-pull-up;
   drive-strength = <20>;
  };

  pcfg_pull_down_4ma: pcfg-pull-down-4ma {
   bias-pull-down;
   drive-strength = <4>;
  };

  pcfg_pull_down_8ma: pcfg-pull-down-8ma {
   bias-pull-down;
   drive-strength = <8>;
  };

  pcfg_pull_down_12ma: pcfg-pull-down-12ma {
   bias-pull-down;
   drive-strength = <12>;
  };

  pcfg_pull_down_18ma: pcfg-pull-down-18ma {
   bias-pull-down;
   drive-strength = <18>;
  };

  pcfg_pull_down_20ma: pcfg-pull-down-20ma {
   bias-pull-down;
   drive-strength = <20>;
  };

  pcfg_output_high: pcfg-output-high {
   output-high;
  };

  pcfg_output_low: pcfg-output-low {
   output-low;
  };

  pcfg_input_enable: pcfg-input-enable {
   input-enable;
  };

  pcfg_input_pull_up: pcfg-input-pull-up {
   input-enable;
   bias-pull-up;
  };

  pcfg_input_pull_down: pcfg-input-pull-down {
   input-enable;
   bias-pull-down;
  };

  clock {
   clk_32k: clk-32k {
    rockchip,pins = <0 0 2 &pcfg_pull_none>;
   };
  };

  cif {
   cif_clkin: cif-clkin {
    rockchip,pins =
     <2 10 3 &pcfg_pull_none>;
   };

   cif_clkouta: cif-clkouta {
    rockchip,pins =
     <2 11 3 &pcfg_pull_none>;
   };
  };

  edp {
   edp_hpd: edp-hpd {
    rockchip,pins =
     <4 23 2 &pcfg_pull_none>;
   };
  };

  gmac {
   rgmii_pins: rgmii-pins {
    rockchip,pins =

     <3 17 1 &pcfg_pull_none_13ma>,

     <3 14 1 &pcfg_pull_none>,

     <3 13 1 &pcfg_pull_none>,

     <3 12 1 &pcfg_pull_none_13ma>,

     <3 11 1 &pcfg_pull_none>,

     <3 9 1 &pcfg_pull_none>,

     <3 8 1 &pcfg_pull_none>,

     <3 7 1 &pcfg_pull_none>,

     <3 6 1 &pcfg_pull_none>,

     <3 5 1 &pcfg_pull_none_13ma>,

     <3 4 1 &pcfg_pull_none_13ma>,

     <3 3 1 &pcfg_pull_none>,

     <3 2 1 &pcfg_pull_none>,

     <3 1 1 &pcfg_pull_none_13ma>,

     <3 0 1 &pcfg_pull_none_13ma>;
   };

   rmii_pins: rmii-pins {
    rockchip,pins =

     <3 13 1 &pcfg_pull_none>,

     <3 12 1 &pcfg_pull_none_13ma>,

     <3 11 1 &pcfg_pull_none>,

     <3 10 1 &pcfg_pull_none>,

     <3 9 1 &pcfg_pull_none>,

     <3 8 1 &pcfg_pull_none>,

     <3 7 1 &pcfg_pull_none>,

     <3 6 1 &pcfg_pull_none>,

     <3 5 1 &pcfg_pull_none_13ma>,

     <3 4 1 &pcfg_pull_none_13ma>;
   };
  };

  i2c0 {
   i2c0_xfer: i2c0-xfer {
    rockchip,pins =
     <1 15 2 &pcfg_pull_none>,
     <1 16 2 &pcfg_pull_none>;
   };
  };

  i2c1 {
   i2c1_xfer: i2c1-xfer {
    rockchip,pins =
     <4 2 1 &pcfg_pull_none>,
     <4 1 1 &pcfg_pull_none>;
   };
  };

  i2c2 {
   i2c2_xfer: i2c2-xfer {
    rockchip,pins =
     <2 1 2 &pcfg_pull_none_12ma>,
     <2 0 2 &pcfg_pull_none_12ma>;
   };
  };

  i2c3 {
   i2c3_xfer: i2c3-xfer {
    rockchip,pins =
     <4 17 1 &pcfg_pull_none>,
     <4 16 1 &pcfg_pull_none>;
   };
  };

  i2c4 {
   i2c4_xfer: i2c4-xfer {
    rockchip,pins =
     <1 12 1 &pcfg_pull_none>,
     <1 11 1 &pcfg_pull_none>;
   };
  };

  i2c5 {
   i2c5_xfer: i2c5-xfer {
    rockchip,pins =
     <3 11 2 &pcfg_pull_none>,
     <3 10 2 &pcfg_pull_none>;
   };
  };

  i2c6 {
   i2c6_xfer: i2c6-xfer {
    rockchip,pins =
     <2 10 2 &pcfg_pull_none>,
     <2 9 2 &pcfg_pull_none>;
   };
  };

  i2c7 {
   i2c7_xfer: i2c7-xfer {
    rockchip,pins =
     <2 8 2 &pcfg_pull_none>,
     <2 7 2 &pcfg_pull_none>;
   };
  };

  i2c8 {
   i2c8_xfer: i2c8-xfer {
    rockchip,pins =
     <1 21 1 &pcfg_pull_none>,
     <1 20 1 &pcfg_pull_none>;
   };
  };

  i2s0 {
   i2s0_2ch_bus: i2s0-2ch-bus {
    rockchip,pins =
     <3 24 1 &pcfg_pull_none>,
     <3 25 1 &pcfg_pull_none>,
     <3 26 1 &pcfg_pull_none>,
     <3 27 1 &pcfg_pull_none>,
     <3 31 1 &pcfg_pull_none>,
     <4 0 1 &pcfg_pull_none>;
   };

   i2s0_2ch_bus_bclk_off: i2s0-2ch-bus-bclk-off {
    rockchip,pins =
     <3 24 0 &pcfg_pull_none>,
     <3 25 1 &pcfg_pull_none>,
     <3 26 1 &pcfg_pull_none>,
     <3 27 1 &pcfg_pull_none>,
     <3 31 1 &pcfg_pull_none>,
     <4 0 1 &pcfg_pull_none>;
   };

   i2s0_8ch_bus: i2s0-8ch-bus {
    rockchip,pins =
     <3 24 1 &pcfg_pull_none>,
     <3 25 1 &pcfg_pull_none>,
     <3 26 1 &pcfg_pull_none>,
     <3 27 1 &pcfg_pull_none>,
     <3 28 1 &pcfg_pull_none>,
     <3 29 1 &pcfg_pull_none>,
     <3 30 1 &pcfg_pull_none>,
     <3 31 1 &pcfg_pull_none>,
     <4 0 1 &pcfg_pull_none>;
   };

   i2s0_8ch_bus_bclk_off: i2s0-8ch-bus-bclk-off {
    rockchip,pins =
     <3 24 0 &pcfg_pull_none>,
     <3 25 1 &pcfg_pull_none>,
     <3 26 1 &pcfg_pull_none>,
     <3 27 1 &pcfg_pull_none>,
     <3 28 1 &pcfg_pull_none>,
     <3 29 1 &pcfg_pull_none>,
     <3 30 1 &pcfg_pull_none>,
     <3 31 1 &pcfg_pull_none>,
     <4 0 1 &pcfg_pull_none>;
   };
  };

  i2s1 {
   i2s1_2ch_bus: i2s1-2ch-bus {
    rockchip,pins =
     <4 3 1 &pcfg_pull_none>,
     <4 4 1 &pcfg_pull_none>,
     <4 5 1 &pcfg_pull_none>,
     <4 6 1 &pcfg_pull_none>,
     <4 7 1 &pcfg_pull_none>;
   };

   i2s1_2ch_bus_bclk_off: i2s1-2ch-bus-bclk-off {
    rockchip,pins =
     <4 3 0 &pcfg_pull_none>,
     <4 4 1 &pcfg_pull_none>,
     <4 5 1 &pcfg_pull_none>,
     <4 6 1 &pcfg_pull_none>,
     <4 7 1 &pcfg_pull_none>;
   };
  };

  sdio0 {
   sdio0_bus1: sdio0-bus1 {
    rockchip,pins =
     <2 20 1 &pcfg_pull_up>;
   };

   sdio0_bus4: sdio0-bus4 {
    rockchip,pins =
     <2 20 1 &pcfg_pull_up>,
     <2 21 1 &pcfg_pull_up>,
     <2 22 1 &pcfg_pull_up>,
     <2 23 1 &pcfg_pull_up>;
   };

   sdio0_cmd: sdio0-cmd {
    rockchip,pins =
     <2 24 1 &pcfg_pull_up>;
   };

   sdio0_clk: sdio0-clk {
    rockchip,pins =
     <2 25 1 &pcfg_pull_none>;
   };

   sdio0_cd: sdio0-cd {
    rockchip,pins =
     <2 26 1 &pcfg_pull_up>;
   };

   sdio0_pwr: sdio0-pwr {
    rockchip,pins =
     <2 27 1 &pcfg_pull_up>;
   };

   sdio0_bkpwr: sdio0-bkpwr {
    rockchip,pins =
     <2 28 1 &pcfg_pull_up>;
   };

   sdio0_wp: sdio0-wp {
    rockchip,pins =
     <0 3 1 &pcfg_pull_up>;
   };

   sdio0_int: sdio0-int {
    rockchip,pins =
     <0 4 1 &pcfg_pull_up>;
   };
  };

  sdmmc {
   sdmmc_bus1: sdmmc-bus1 {
    rockchip,pins =
     <4 8 1 &pcfg_pull_up>;
   };

   sdmmc_bus4: sdmmc-bus4 {
    rockchip,pins =
     <4 8 1 &pcfg_pull_up>,
     <4 9 1 &pcfg_pull_up>,
     <4 10 1 &pcfg_pull_up>,
     <4 11 1 &pcfg_pull_up>;
   };

   sdmmc_clk: sdmmc-clk {
    rockchip,pins =
     <4 12 1 &pcfg_pull_none>;
   };

   sdmmc_cmd: sdmmc-cmd {
    rockchip,pins =
     <4 13 1 &pcfg_pull_up>;
   };

   sdmmc_cd: sdmmc-cd {
    rockchip,pins =
     <0 7 1 &pcfg_pull_up>;
   };

   sdmmc_wp: sdmmc-wp {
    rockchip,pins =
     <0 8 1 &pcfg_pull_up>;
   };
  };

  suspend {
   ap_pwroff: ap-pwroff {
    rockchip,pins = <1 5 1 &pcfg_pull_none>;
   };

   ddrio_pwroff: ddrio-pwroff {
    rockchip,pins = <0 1 1 &pcfg_pull_none>;
   };
  };

  spdif {
   spdif_bus: spdif-bus {
    rockchip,pins =
     <4 21 1 &pcfg_pull_none>;
   };

   spdif_bus_1: spdif-bus-1 {
    rockchip,pins =
     <3 16 3 &pcfg_pull_none>;
   };
  };

  spi0 {
   spi0_clk: spi0-clk {
    rockchip,pins =
     <3 6 2 &pcfg_pull_up>;
   };
   spi0_cs0: spi0-cs0 {
    rockchip,pins =
     <3 7 2 &pcfg_pull_up>;
   };
   spi0_cs1: spi0-cs1 {
    rockchip,pins =
     <3 8 2 &pcfg_pull_up>;
   };
   spi0_tx: spi0-tx {
    rockchip,pins =
     <3 5 2 &pcfg_pull_up>;
   };
   spi0_rx: spi0-rx {
    rockchip,pins =
     <3 4 2 &pcfg_pull_up>;
   };
  };

  spi1 {
   spi1_clk: spi1-clk {
    rockchip,pins =
     <1 9 2 &pcfg_pull_up>;
   };
   spi1_cs0: spi1-cs0 {
    rockchip,pins =
     <1 10 2 &pcfg_pull_up>;
   };
   spi1_rx: spi1-rx {
    rockchip,pins =
     <1 7 2 &pcfg_pull_up>;
   };
   spi1_tx: spi1-tx {
    rockchip,pins =
     <1 8 2 &pcfg_pull_up>;
   };
  };

  spi2 {
   spi2_clk: spi2-clk {
    rockchip,pins =
     <2 11 1 &pcfg_pull_up>;
   };
   spi2_cs0: spi2-cs0 {
    rockchip,pins =
     <2 12 1 &pcfg_pull_up>;
   };
   spi2_rx: spi2-rx {
    rockchip,pins =
     <2 9 1 &pcfg_pull_up>;
   };
   spi2_tx: spi2-tx {
    rockchip,pins =
     <2 10 1 &pcfg_pull_up>;
   };
  };

  spi3 {
   spi3_clk: spi3-clk {
    rockchip,pins =
     <1 17 1 &pcfg_pull_up>;
   };
   spi3_cs0: spi3-cs0 {
    rockchip,pins =
     <1 18 1 &pcfg_pull_up>;
   };
   spi3_rx: spi3-rx {
    rockchip,pins =
     <1 15 1 &pcfg_pull_up>;
   };
   spi3_tx: spi3-tx {
    rockchip,pins =
     <1 16 1 &pcfg_pull_up>;
   };
  };

  spi4 {
   spi4_clk: spi4-clk {
    rockchip,pins =
     <3 2 2 &pcfg_pull_up>;
   };
   spi4_cs0: spi4-cs0 {
    rockchip,pins =
     <3 3 2 &pcfg_pull_up>;
   };
   spi4_rx: spi4-rx {
    rockchip,pins =
     <3 0 2 &pcfg_pull_up>;
   };
   spi4_tx: spi4-tx {
    rockchip,pins =
     <3 1 2 &pcfg_pull_up>;
   };
  };

  spi5 {
   spi5_clk: spi5-clk {
    rockchip,pins =
     <2 22 2 &pcfg_pull_up>;
   };
   spi5_cs0: spi5-cs0 {
    rockchip,pins =
     <2 23 2 &pcfg_pull_up>;
   };
   spi5_rx: spi5-rx {
    rockchip,pins =
     <2 20 2 &pcfg_pull_up>;
   };
   spi5_tx: spi5-tx {
    rockchip,pins =
     <2 21 2 &pcfg_pull_up>;
   };
  };

  testclk {
   test_clkout0: test-clkout0 {
    rockchip,pins =
     <0 0 1 &pcfg_pull_none>;
   };

   test_clkout1: test-clkout1 {
    rockchip,pins =
     <2 25 2 &pcfg_pull_none>;
   };

   test_clkout2: test-clkout2 {
    rockchip,pins =
     <0 8 3 &pcfg_pull_none>;
   };
  };

  tsadc {
   otp_pin: otp-pin {
    rockchip,pins = <1 6 0 &pcfg_pull_none>;
   };

   otp_out: otp-out {
    rockchip,pins = <1 6 1 &pcfg_pull_none>;
   };
  };

  uart0 {
   uart0_xfer: uart0-xfer {
    rockchip,pins =
     <2 16 1 &pcfg_pull_up>,
     <2 17 1 &pcfg_pull_none>;
   };

   uart0_cts: uart0-cts {
    rockchip,pins =
     <2 18 1 &pcfg_pull_none>;
   };

   uart0_rts: uart0-rts {
    rockchip,pins =
     <2 19 1 &pcfg_pull_none>;
   };
  };

  uart1 {
   uart1_xfer: uart1-xfer {
    rockchip,pins =
     <3 12 2 &pcfg_pull_up>,
     <3 13 2 &pcfg_pull_none>;
   };
  };

  uart2a {
   uart2a_xfer: uart2a-xfer {
    rockchip,pins =
     <4 8 2 &pcfg_pull_up>,
     <4 9 2 &pcfg_pull_none>;
   };
  };

  uart2b {
   uart2b_xfer: uart2b-xfer {
    rockchip,pins =
     <4 16 2 &pcfg_pull_up>,
     <4 17 2 &pcfg_pull_none>;
   };
  };

  uart2c {
   uart2c_xfer: uart2c-xfer {
    rockchip,pins =
     <4 19 1 &pcfg_pull_up>,
     <4 20 1 &pcfg_pull_none>;
   };
  };

  uart3 {
   uart3_xfer: uart3-xfer {
    rockchip,pins =
     <3 14 2 &pcfg_pull_up>,
     <3 15 2 &pcfg_pull_none>;
   };

   uart3_cts: uart3-cts {
    rockchip,pins =
     <3 16 2 &pcfg_pull_none>;
   };

   uart3_rts: uart3-rts {
    rockchip,pins =
     <3 17 2 &pcfg_pull_none>;
   };
  };

  uart4 {
   uart4_xfer: uart4-xfer {
    rockchip,pins =
     <1 7 1 &pcfg_pull_up>,
     <1 8 1 &pcfg_pull_none>;
   };
  };

  uarthdcp {
   uarthdcp_xfer: uarthdcp-xfer {
    rockchip,pins =
     <4 21 2 &pcfg_pull_up>,
     <4 22 2 &pcfg_pull_none>;
   };
  };

  pwm0 {
   pwm0_pin: pwm0-pin {
    rockchip,pins =
     <4 18 1 &pcfg_pull_none>;
   };

   pwm0_pin_pull_down: pwm0-pin-pull-down {
    rockchip,pins =
     <4 18 1 &pcfg_pull_down>;
   };

   vop0_pwm_pin: vop0-pwm-pin {
    rockchip,pins =
     <4 18 2 &pcfg_pull_none>;
   };

   vop1_pwm_pin: vop1-pwm-pin {
    rockchip,pins =
     <4 18 3 &pcfg_pull_none>;
   };
  };

  pwm1 {
   pwm1_pin: pwm1-pin {
    rockchip,pins =
     <4 22 1 &pcfg_pull_none>;
   };

   pwm1_pin_pull_down: pwm1-pin-pull-down {
    rockchip,pins =
     <4 22 1 &pcfg_pull_down>;
   };
  };

  pwm2 {
   pwm2_pin: pwm2-pin {
    rockchip,pins =
     <1 19 1 &pcfg_pull_none>;
   };

   pwm2_pin_pull_down: pwm2-pin-pull-down {
    rockchip,pins =
     <1 19 1 &pcfg_pull_down>;
   };
  };

  pwm3a {
   pwm3a_pin: pwm3a-pin {
    rockchip,pins =
     <0 6 1 &pcfg_pull_none>;
   };
  };

  pwm3b {
   pwm3b_pin: pwm3b-pin {
    rockchip,pins =
     <1 14 1 &pcfg_pull_none>;
   };
  };

  hdmi {
   hdmi_i2c_xfer: hdmi-i2c-xfer {
    rockchip,pins =
     <4 17 3 &pcfg_pull_none>,
     <4 16 3 &pcfg_pull_none>;
   };

   hdmi_cec: hdmi-cec {
    rockchip,pins =
     <4 23 1 &pcfg_pull_none>;
   };
  };

  pcie {
   pcie_clkreqn_cpm: pci-clkreqn-cpm {
    rockchip,pins =
     <2 26 0 &pcfg_pull_none>;
   };

   pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
    rockchip,pins =
     <4 24 0 &pcfg_pull_none>;
   };
  };

 };
};
# 9 "arch/arm64/boot/dts/rockchip/rk3399-evb.dts" 2

/ {
 model = "Rockchip RK3399 Evaluation Board";
 compatible = "rockchip,rk3399-evb", "rockchip,rk3399";

 aliases {
  mmc0 = &sdhci;
 };

 backlight: backlight {
  compatible = "pwm-backlight";
  brightness-levels = <
     0 1 2 3 4 5 6 7
     8 9 10 11 12 13 14 15
    16 17 18 19 20 21 22 23
    24 25 26 27 28 29 30 31
    32 33 34 35 36 37 38 39
    40 41 42 43 44 45 46 47
    48 49 50 51 52 53 54 55
    56 57 58 59 60 61 62 63
    64 65 66 67 68 69 70 71
    72 73 74 75 76 77 78 79
    80 81 82 83 84 85 86 87
    88 89 90 91 92 93 94 95
    96 97 98 99 100 101 102 103
   104 105 106 107 108 109 110 111
   112 113 114 115 116 117 118 119
   120 121 122 123 124 125 126 127
   128 129 130 131 132 133 134 135
   136 137 138 139 140 141 142 143
   144 145 146 147 148 149 150 151
   152 153 154 155 156 157 158 159
   160 161 162 163 164 165 166 167
   168 169 170 171 172 173 174 175
   176 177 178 179 180 181 182 183
   184 185 186 187 188 189 190 191
   192 193 194 195 196 197 198 199
   200 201 202 203 204 205 206 207
   208 209 210 211 212 213 214 215
   216 217 218 219 220 221 222 223
   224 225 226 227 228 229 230 231
   232 233 234 235 236 237 238 239
   240 241 242 243 244 245 246 247
   248 249 250 251 252 253 254 255>;
  default-brightness-level = <200>;
  pwms = <&pwm0 0 25000 0>;
 };

 edp_panel: edp-panel {
  compatible = "lg,lp079qx1-sp0v";
  backlight = <&backlight>;
  enable-gpios = <&gpio1 13 0>;
  power-supply = <&vcc3v3_s0>;

  port {
   panel_in_edp: endpoint {
    remote-endpoint = <&edp_out_panel>;
   };
  };
 };

 clkin_gmac: external-gmac-clock {
  compatible = "fixed-clock";
  clock-frequency = <125000000>;
  clock-output-names = "clkin_gmac";
  #clock-cells = <0>;
 };

 vdd_center: vdd-center {
  compatible = "pwm-regulator";
  pwms = <&pwm3 0 25000 0>;
  regulator-name = "vdd_center";
  regulator-min-microvolt = <800000>;
  regulator-max-microvolt = <1400000>;
  regulator-always-on;
  regulator-boot-on;
  status = "okay";
 };

 vcc3v3_sys: vcc3v3-sys {
  compatible = "regulator-fixed";
  regulator-name = "vcc3v3_sys";
  regulator-always-on;
  regulator-boot-on;
  regulator-min-microvolt = <3300000>;
  regulator-max-microvolt = <3300000>;
 };

 vcc5v0_sys: vcc5v0-sys {
  compatible = "regulator-fixed";
  regulator-name = "vcc5v0_sys";
  regulator-always-on;
  regulator-boot-on;
  regulator-min-microvolt = <5000000>;
  regulator-max-microvolt = <5000000>;
 };

 vcc5v0_host: vcc5v0-host-regulator {
  compatible = "regulator-fixed";
  enable-active-high;
  gpio = <&gpio4 25 0>;
  pinctrl-names = "default";
  pinctrl-0 = <&vcc5v0_host_en>;
  regulator-name = "vcc5v0_host";
  vin-supply = <&vcc5v0_sys>;
 };

 vcc_phy: vcc-phy-regulator {
  compatible = "regulator-fixed";
  regulator-name = "vcc_phy";
  regulator-always-on;
  regulator-boot-on;
 };

 vcc_phy: vcc-phy-regulator {
  compatible = "regulator-fixed";
  regulator-name = "vcc_phy";
  regulator-always-on;
  regulator-boot-on;
 };

};

&edp {
 status = "okay";
 force-hpd;

 ports {
  edp_out: port@1 {
   reg = <1>;
   #address-cells = <1>;
   #size-cells = <0>;

   edp_out_panel: endpoint@0 {
    reg = <0>;
    remote-endpoint = <&panel_in_edp>;
   };
  };
 };
};

&emmc_phy {
 status = "okay";
};

&gmac {
 assigned-clocks = <&cru 166>;
 assigned-clock-parents = <&clkin_gmac>;
 clock_in_out = "input";
 phy-supply = <&vcc_phy>;
 phy-mode = "rgmii";
 pinctrl-names = "default";
 pinctrl-0 = <&rgmii_pins>;
 snps,reset-gpio = <&gpio3 15 1>;
 snps,reset-active-low;
 snps,reset-delays-us = <0 10000 50000>;
 tx_delay = <0x28>;
 rx_delay = <0x11>;
 status = "okay";
};

&i2c0 {
 status = "okay";

 rk808: pmic@1b {
  compatible = "rockchip,rk808";
  reg = <0x1b>;
  interrupt-parent = <&gpio1>;
  interrupts = <21 8>;
  pinctrl-names = "default";
  pinctrl-0 = <&pmic_int_l>;
  rockchip,system-power-controller;
  wakeup-source;
  #clock-cells = <1>;
  clock-output-names = "rk808-clkout1", "rk808-clkout2";

  vcc1-supply = <&vcc3v3_sys>;
  vcc2-supply = <&vcc3v3_sys>;
  vcc3-supply = <&vcc3v3_sys>;
  vcc4-supply = <&vcc3v3_sys>;
  vcc6-supply = <&vcc3v3_sys>;
  vcc7-supply = <&vcc3v3_sys>;
  vcc8-supply = <&vcc3v3_sys>;
  vcc9-supply = <&vcc3v3_sys>;
  vcc10-supply = <&vcc3v3_sys>;
  vcc11-supply = <&vcc3v3_sys>;
  vcc12-supply = <&vcc3v3_sys>;
  vddio-supply = <&vcc1v8_pmu>;

  regulators {
   vdd_log: DCDC_REG1 {
    regulator-name = "vdd_log";
    regulator-min-microvolt = <750000>;
    regulator-max-microvolt = <1350000>;
    regulator-ramp-delay = <6001>;
    regulator-always-on;
    regulator-boot-on;
    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <900000>;
    };
   };

   vdd_cpu_l: DCDC_REG2 {
    regulator-name = "vdd_cpu_l";
    regulator-min-microvolt = <750000>;
    regulator-max-microvolt = <1350000>;
    regulator-ramp-delay = <6001>;
    regulator-always-on;
    regulator-boot-on;
    regulator-state-mem {
     regulator-off-in-suspend;
    };
   };

   vcc_ddr: DCDC_REG3 {
    regulator-name = "vcc_ddr";
    regulator-always-on;
    regulator-boot-on;
    regulator-state-mem {
     regulator-on-in-suspend;
    };
   };

   vcc_1v8: DCDC_REG4 {
    regulator-name = "vcc_1v8";
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <1800000>;
    regulator-always-on;
    regulator-boot-on;
    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <1800000>;
    };
   };

   vcc1v8_dvp: LDO_REG1 {
    regulator-name = "vcc1v8_dvp";
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <1800000>;
    regulator-always-on;
    regulator-boot-on;
    regulator-state-mem {
     regulator-off-in-suspend;
    };
   };

   vcc3v0_tp: LDO_REG2 {
    regulator-name = "vcc3v0_tp";
    regulator-min-microvolt = <3000000>;
    regulator-max-microvolt = <3000000>;
    regulator-always-on;
    regulator-boot-on;
    regulator-state-mem {
     regulator-off-in-suspend;
    };
   };

   vcc1v8_pmu: LDO_REG3 {
    regulator-name = "vcc1v8_pmu";
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <1800000>;
    regulator-always-on;
    regulator-boot-on;
    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <1800000>;
    };
   };

   vcc_sd: LDO_REG4 {
    regulator-name = "vcc_sd";
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <3000000>;
    regulator-always-on;
    regulator-boot-on;
    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <3000000>;
    };
   };

   vcca3v0_codec: LDO_REG5 {
    regulator-name = "vcca3v0_codec";
    regulator-min-microvolt = <3000000>;
    regulator-max-microvolt = <3000000>;
    regulator-always-on;
    regulator-boot-on;
    regulator-state-mem {
     regulator-off-in-suspend;
    };
   };

   vcc_1v5: LDO_REG6 {
    regulator-name = "vcc_1v5";
    regulator-min-microvolt = <1500000>;
    regulator-max-microvolt = <1500000>;
    regulator-always-on;
    regulator-boot-on;
    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <1500000>;
    };
   };

   vcca1v8_codec: LDO_REG7 {
    regulator-name = "vcca1v8_codec";
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <1800000>;
    regulator-always-on;
    regulator-boot-on;
    regulator-state-mem {
     regulator-off-in-suspend;
    };
   };

   vcc_3v0: LDO_REG8 {
    regulator-name = "vcc_3v0";
    regulator-min-microvolt = <3000000>;
    regulator-max-microvolt = <3000000>;
    regulator-always-on;
    regulator-boot-on;
    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <3000000>;
    };
   };

   vcc3v3_s3: SWITCH_REG1 {
    regulator-name = "vcc3v3_s3";
    regulator-always-on;
    regulator-boot-on;
    regulator-state-mem {
     regulator-on-in-suspend;
    };
   };

   vcc3v3_s0: SWITCH_REG2 {
    regulator-name = "vcc3v3_s0";
    regulator-always-on;
    regulator-boot-on;
    regulator-state-mem {
     regulator-off-in-suspend;
    };
   };
  };
 };

 vdd_cpu_b: regulator@40 {
  compatible = "silergy,syr827";
  reg = <0x40>;
  fcs,suspend-voltage-selector = <1>;
  regulator-name = "vdd_cpu_b";
  regulator-min-microvolt = <712500>;
  regulator-max-microvolt = <1500000>;
  regulator-ramp-delay = <1000>;
  regulator-always-on;
  regulator-boot-on;
  vin-supply = <&vcc5v0_sys>;

  regulator-state-mem {
   regulator-off-in-suspend;
  };
 };

 vdd_gpu: regulator@41 {
  compatible = "silergy,syr828";
  reg = <0x41>;
  fcs,suspend-voltage-selector = <1>;
  regulator-name = "vdd_gpu";
  regulator-min-microvolt = <712500>;
  regulator-max-microvolt = <1500000>;
  regulator-ramp-delay = <1000>;
  regulator-always-on;
  regulator-boot-on;
  vin-supply = <&vcc5v0_sys>;

  regulator-state-mem {
   regulator-off-in-suspend;
  };
 };
};

&pwm0 {
 status = "okay";
};

&pwm2 {
 status = "okay";
};

&pwm3 {
 status = "okay";
};

&sdhci {
 bus-width = <8>;
 mmc-hs400-1_8v;
 mmc-hs400-enhanced-strobe;
 non-removable;
 status = "okay";
};

&pcie_phy {
 status = "disabled";
};

&pcie0 {
 ep-gpios = <&gpio3 13 0>;
 num-lanes = <4>;
 pinctrl-names = "default";
 pinctrl-0 = <&pcie_clkreqn_cpm>;
 status = "disabled";
};

&u2phy0 {
 status = "okay";
};

&u2phy0_host {
 phy-supply = <&vcc5v0_host>;
 status = "okay";
};

&u2phy1 {
 status = "okay";
};

&u2phy1_host {
 phy-supply = <&vcc5v0_host>;
 status = "okay";
};

&uart2 {
 status = "okay";
};

&usb_host0_ehci {
 status = "okay";
};

&usb_host0_ohci {
 status = "okay";
};

&usb_host1_ehci {
 status = "okay";
};

&usb_host1_ohci {
 status = "okay";
};

&pinctrl {
 pmic {
  pmic_int_l: pmic-int-l {
   rockchip,pins =
    <1 21 0 &pcfg_pull_up>;
  };
 };

 usb2 {
  vcc5v0_host_en: vcc5v0-host-en {
   rockchip,pins =
    <4 25 0 &pcfg_pull_none>;
  };
 };
};

&vopb {
 status = "okay";
};

&vopb_mmu {
 status = "okay";
};