# 0 "arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts"
# 0 "<built-in>"
# 0 "<command-line>"
# 1 "arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts"





/dts-v1/;
# 1 "arch/arm64/boot/dts/rockchip/rk3368.dtsi" 1





# 1 "./scripts/dtc/include-prefixes/dt-bindings/clock/rk3368-cru.h" 1
# 7 "arch/arm64/boot/dts/rockchip/rk3368.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/gpio/gpio.h" 1
# 8 "arch/arm64/boot/dts/rockchip/rk3368.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/irq.h" 1
# 9 "arch/arm64/boot/dts/rockchip/rk3368.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h" 1
# 10 "arch/arm64/boot/dts/rockchip/rk3368.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/pinctrl/rockchip.h" 1
# 11 "arch/arm64/boot/dts/rockchip/rk3368.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/power/rk3368-power.h" 1
# 12 "arch/arm64/boot/dts/rockchip/rk3368.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/soc/rockchip,boot-mode.h" 1
# 13 "arch/arm64/boot/dts/rockchip/rk3368.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/thermal/thermal.h" 1
# 14 "arch/arm64/boot/dts/rockchip/rk3368.dtsi" 2

/ {
 compatible = "rockchip,rk3368";
 interrupt-parent = <&gic>;
 #address-cells = <2>;
 #size-cells = <2>;

 aliases {
  ethernet0 = &gmac;
  i2c0 = &i2c0;
  i2c1 = &i2c1;
  i2c2 = &i2c2;
  i2c3 = &i2c3;
  i2c4 = &i2c4;
  i2c5 = &i2c5;
  serial0 = &uart0;
  serial1 = &uart1;
  serial2 = &uart2;
  serial3 = &uart3;
  serial4 = &uart4;
  spi0 = &spi0;
  spi1 = &spi1;
  spi2 = &spi2;
 };

 cpus {
  #address-cells = <0x2>;
  #size-cells = <0x0>;

  cpu-map {
   cluster0 {
    core0 {
     cpu = <&cpu_b0>;
    };
    core1 {
     cpu = <&cpu_b1>;
    };
    core2 {
     cpu = <&cpu_b2>;
    };
    core3 {
     cpu = <&cpu_b3>;
    };
   };

   cluster1 {
    core0 {
     cpu = <&cpu_l0>;
    };
    core1 {
     cpu = <&cpu_l1>;
    };
    core2 {
     cpu = <&cpu_l2>;
    };
    core3 {
     cpu = <&cpu_l3>;
    };
   };
  };

  cpu_l0: cpu@0 {
   device_type = "cpu";
   compatible = "arm,cortex-a53";
   reg = <0x0 0x0>;
   enable-method = "psci";
   #cooling-cells = <2>;
  };

  cpu_l1: cpu@1 {
   device_type = "cpu";
   compatible = "arm,cortex-a53";
   reg = <0x0 0x1>;
   enable-method = "psci";
   #cooling-cells = <2>;
  };

  cpu_l2: cpu@2 {
   device_type = "cpu";
   compatible = "arm,cortex-a53";
   reg = <0x0 0x2>;
   enable-method = "psci";
   #cooling-cells = <2>;
  };

  cpu_l3: cpu@3 {
   device_type = "cpu";
   compatible = "arm,cortex-a53";
   reg = <0x0 0x3>;
   enable-method = "psci";
   #cooling-cells = <2>;
  };

  cpu_b0: cpu@100 {
   device_type = "cpu";
   compatible = "arm,cortex-a53";
   reg = <0x0 0x100>;
   enable-method = "psci";
   #cooling-cells = <2>;
  };

  cpu_b1: cpu@101 {
   device_type = "cpu";
   compatible = "arm,cortex-a53";
   reg = <0x0 0x101>;
   enable-method = "psci";
   #cooling-cells = <2>;
  };

  cpu_b2: cpu@102 {
   device_type = "cpu";
   compatible = "arm,cortex-a53";
   reg = <0x0 0x102>;
   enable-method = "psci";
   #cooling-cells = <2>;
  };

  cpu_b3: cpu@103 {
   device_type = "cpu";
   compatible = "arm,cortex-a53";
   reg = <0x0 0x103>;
   enable-method = "psci";
   #cooling-cells = <2>;
  };
 };

 arm-pmu {
  compatible = "arm,armv8-pmuv3";
  interrupts = <0 112 4>,
        <0 113 4>,
        <0 114 4>,
        <0 115 4>,
        <0 116 4>,
        <0 117 4>,
        <0 118 4>,
        <0 119 4>;
  interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
         <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
         <&cpu_b2>, <&cpu_b3>;
 };

 psci {
  compatible = "arm,psci-0.2";
  method = "smc";
 };

 timer {
  compatible = "arm,armv8-timer";
  interrupts = <1 13
   ((((1 << (8)) - 1) << 8) | 4)>,
        <1 14
   ((((1 << (8)) - 1) << 8) | 4)>,
        <1 11
   ((((1 << (8)) - 1) << 8) | 4)>,
        <1 10
   ((((1 << (8)) - 1) << 8) | 4)>;
 };

 xin24m: oscillator {
  compatible = "fixed-clock";
  clock-frequency = <24000000>;
  clock-output-names = "xin24m";
  #clock-cells = <0>;
 };

 sdmmc: mmc@ff0c0000 {
  compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
  reg = <0x0 0xff0c0000 0x0 0x4000>;
  max-frequency = <150000000>;
  clocks = <&cru 456>, <&cru 68>,
    <&cru 114>, <&cru 118>;
  clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  fifo-depth = <0x100>;
  interrupts = <0 32 4>;
  resets = <&cru 128>;
  reset-names = "reset";
  status = "disabled";
 };

 sdio0: mmc@ff0d0000 {
  compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
  reg = <0x0 0xff0d0000 0x0 0x4000>;
  max-frequency = <150000000>;
  clocks = <&cru 457>, <&cru 69>,
    <&cru 115>, <&cru 119>;
  clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  fifo-depth = <0x100>;
  interrupts = <0 33 4>;
  resets = <&cru 129>;
  reset-names = "reset";
  status = "disabled";
 };

 emmc: mmc@ff0f0000 {
  compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
  reg = <0x0 0xff0f0000 0x0 0x4000>;
  max-frequency = <150000000>;
  clocks = <&cru 459>, <&cru 71>,
    <&cru 117>, <&cru 121>;
  clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  fifo-depth = <0x100>;
  interrupts = <0 35 4>;
  resets = <&cru 131>;
  reset-names = "reset";
  status = "disabled";
 };

 saradc: saradc@ff100000 {
  compatible = "rockchip,saradc";
  reg = <0x0 0xff100000 0x0 0x100>;
  interrupts = <0 36 4>;
  #io-channel-cells = <1>;
  clocks = <&cru 73>, <&cru 347>;
  clock-names = "saradc", "apb_pclk";
  resets = <&cru 87>;
  reset-names = "saradc-apb";
  status = "disabled";
 };

 spi0: spi@ff110000 {
  compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
  reg = <0x0 0xff110000 0x0 0x1000>;
  clocks = <&cru 65>, <&cru 338>;
  clock-names = "spiclk", "apb_pclk";
  interrupts = <0 44 4>;
  pinctrl-names = "default";
  pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 spi1: spi@ff120000 {
  compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
  reg = <0x0 0xff120000 0x0 0x1000>;
  clocks = <&cru 66>, <&cru 339>;
  clock-names = "spiclk", "apb_pclk";
  interrupts = <0 45 4>;
  pinctrl-names = "default";
  pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 spi2: spi@ff130000 {
  compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
  reg = <0x0 0xff130000 0x0 0x1000>;
  clocks = <&cru 67>, <&cru 340>;
  clock-names = "spiclk", "apb_pclk";
  interrupts = <0 41 4>;
  pinctrl-names = "default";
  pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c2: i2c@ff140000 {
  compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
  reg = <0x0 0xff140000 0x0 0x1000>;
  interrupts = <0 62 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  clock-names = "i2c";
  clocks = <&cru 334>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c2_xfer>;
  status = "disabled";
 };

 i2c3: i2c@ff150000 {
  compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
  reg = <0x0 0xff150000 0x0 0x1000>;
  interrupts = <0 63 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  clock-names = "i2c";
  clocks = <&cru 335>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c3_xfer>;
  status = "disabled";
 };

 i2c4: i2c@ff160000 {
  compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
  reg = <0x0 0xff160000 0x0 0x1000>;
  interrupts = <0 64 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  clock-names = "i2c";
  clocks = <&cru 336>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c4_xfer>;
  status = "disabled";
 };

 i2c5: i2c@ff170000 {
  compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
  reg = <0x0 0xff170000 0x0 0x1000>;
  interrupts = <0 65 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  clock-names = "i2c";
  clocks = <&cru 337>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c5_xfer>;
  status = "disabled";
 };

 uart0: serial@ff180000 {
  compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
  reg = <0x0 0xff180000 0x0 0x100>;
  clock-frequency = <24000000>;
  clocks = <&cru 77>, <&cru 341>;
  clock-names = "baudclk", "apb_pclk";
  interrupts = <0 55 4>;
  reg-shift = <2>;
  reg-io-width = <4>;
  status = "disabled";
 };

 uart1: serial@ff190000 {
  compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
  reg = <0x0 0xff190000 0x0 0x100>;
  clock-frequency = <24000000>;
  clocks = <&cru 78>, <&cru 342>;
  clock-names = "baudclk", "apb_pclk";
  interrupts = <0 56 4>;
  reg-shift = <2>;
  reg-io-width = <4>;
  status = "disabled";
 };

 uart3: serial@ff1b0000 {
  compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
  reg = <0x0 0xff1b0000 0x0 0x100>;
  clock-frequency = <24000000>;
  clocks = <&cru 80>, <&cru 344>;
  clock-names = "baudclk", "apb_pclk";
  interrupts = <0 58 4>;
  reg-shift = <2>;
  reg-io-width = <4>;
  status = "disabled";
 };

 uart4: serial@ff1c0000 {
  compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
  reg = <0x0 0xff1c0000 0x0 0x100>;
  clock-frequency = <24000000>;
  clocks = <&cru 81>, <&cru 345>;
  clock-names = "baudclk", "apb_pclk";
  interrupts = <0 59 4>;
  reg-shift = <2>;
  reg-io-width = <4>;
  status = "disabled";
 };

 dmac_peri: dma-controller@ff250000 {
  compatible = "arm,pl330", "arm,primecell";
  reg = <0x0 0xff250000 0x0 0x4000>;
  interrupts = <0 2 4>,
        <0 3 4>;
  #dma-cells = <1>;
  arm,pl330-broken-no-flushp;
  arm,pl330-periph-burst;
  clocks = <&cru 195>;
  clock-names = "apb_pclk";
 };

 thermal-zones {
  cpu_thermal: cpu-thermal {
   polling-delay-passive = <100>;
   polling-delay = <5000>;

   thermal-sensors = <&tsadc 0>;

   trips {
    cpu_alert0: cpu_alert0 {
     temperature = <75000>;
     hysteresis = <2000>;
     type = "passive";
    };
    cpu_alert1: cpu_alert1 {
     temperature = <80000>;
     hysteresis = <2000>;
     type = "passive";
    };
    cpu_crit: cpu_crit {
     temperature = <95000>;
     hysteresis = <2000>;
     type = "critical";
    };
   };

   cooling-maps {
    map0 {
     trip = <&cpu_alert0>;
     cooling-device =
     <&cpu_b0 (~0) (~0)>,
     <&cpu_b1 (~0) (~0)>,
     <&cpu_b2 (~0) (~0)>,
     <&cpu_b3 (~0) (~0)>;
    };
    map1 {
     trip = <&cpu_alert1>;
     cooling-device =
     <&cpu_l0 (~0) (~0)>,
     <&cpu_l1 (~0) (~0)>,
     <&cpu_l2 (~0) (~0)>,
     <&cpu_l3 (~0) (~0)>;
    };
   };
  };

  gpu_thermal: gpu-thermal {
   polling-delay-passive = <100>;
   polling-delay = <5000>;

   thermal-sensors = <&tsadc 1>;

   trips {
    gpu_alert0: gpu_alert0 {
     temperature = <80000>;
     hysteresis = <2000>;
     type = "passive";
    };
    gpu_crit: gpu_crit {
     temperature = <115000>;
     hysteresis = <2000>;
     type = "critical";
    };
   };

   cooling-maps {
    map0 {
     trip = <&gpu_alert0>;
     cooling-device =
     <&cpu_b0 (~0) (~0)>,
     <&cpu_b1 (~0) (~0)>,
     <&cpu_b2 (~0) (~0)>,
     <&cpu_b3 (~0) (~0)>;
    };
   };
  };
 };

 tsadc: tsadc@ff280000 {
  compatible = "rockchip,rk3368-tsadc";
  reg = <0x0 0xff280000 0x0 0x100>;
  interrupts = <0 37 4>;
  clocks = <&cru 72>, <&cru 346>;
  clock-names = "tsadc", "apb_pclk";
  resets = <&cru 159>;
  reset-names = "tsadc-apb";
  pinctrl-names = "init", "default", "sleep";
  pinctrl-0 = <&otp_pin>;
  pinctrl-1 = <&otp_out>;
  pinctrl-2 = <&otp_pin>;
  #thermal-sensor-cells = <1>;
  rockchip,hw-tshut-temp = <95000>;
  status = "disabled";
 };

 gmac: ethernet@ff290000 {
  compatible = "rockchip,rk3368-gmac";
  reg = <0x0 0xff290000 0x0 0x10000>;
  interrupts = <0 27 4>;
  interrupt-names = "macirq";
  rockchip,grf = <&grf>;
  clocks = <&cru 127>,
   <&cru 102>, <&cru 103>,
   <&cru 99>, <&cru 128>,
   <&cru 197>, <&cru 349>;
  clock-names = "stmmaceth",
   "mac_clk_rx", "mac_clk_tx",
   "clk_mac_ref", "clk_mac_refout",
   "aclk_mac", "pclk_mac";
  status = "disabled";
 };

 usb_host0_ehci: usb@ff500000 {
  compatible = "generic-ehci";
  reg = <0x0 0xff500000 0x0 0x100>;
  interrupts = <0 24 4>;
  clocks = <&cru 450>;
  status = "disabled";
 };

 usb_otg: usb@ff580000 {
  compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
    "snps,dwc2";
  reg = <0x0 0xff580000 0x0 0x40000>;
  interrupts = <0 23 4>;
  clocks = <&cru 449>;
  clock-names = "otg";
  dr_mode = "otg";
  g-np-tx-fifo-size = <16>;
  g-rx-fifo-size = <275>;
  g-tx-fifo-size = <256 128 128 64 64 32>;
  status = "disabled";
 };

 dmac_bus: dma-controller@ff600000 {
  compatible = "arm,pl330", "arm,primecell";
  reg = <0x0 0xff600000 0x0 0x4000>;
  interrupts = <0 0 4>,
        <0 1 4>;
  #dma-cells = <1>;
  arm,pl330-broken-no-flushp;
  arm,pl330-periph-burst;
  clocks = <&cru 194>;
  clock-names = "apb_pclk";
 };

 i2c0: i2c@ff650000 {
  compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
  reg = <0x0 0xff650000 0x0 0x1000>;
  clocks = <&cru 332>;
  clock-names = "i2c";
  interrupts = <0 60 4>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c0_xfer>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c1: i2c@ff660000 {
  compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
  reg = <0x0 0xff660000 0x0 0x1000>;
  interrupts = <0 61 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  clock-names = "i2c";
  clocks = <&cru 333>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c1_xfer>;
  status = "disabled";
 };

 pwm0: pwm@ff680000 {
  compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
  reg = <0x0 0xff680000 0x0 0x10>;
  #pwm-cells = <3>;
  pinctrl-names = "default";
  pinctrl-0 = <&pwm0_pin>;
  clocks = <&cru 351>;
  status = "disabled";
 };

 pwm1: pwm@ff680010 {
  compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
  reg = <0x0 0xff680010 0x0 0x10>;
  #pwm-cells = <3>;
  pinctrl-names = "default";
  pinctrl-0 = <&pwm1_pin>;
  clocks = <&cru 351>;
  status = "disabled";
 };

 pwm2: pwm@ff680020 {
  compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
  reg = <0x0 0xff680020 0x0 0x10>;
  #pwm-cells = <3>;
  clocks = <&cru 351>;
  status = "disabled";
 };

 pwm3: pwm@ff680030 {
  compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
  reg = <0x0 0xff680030 0x0 0x10>;
  #pwm-cells = <3>;
  pinctrl-names = "default";
  pinctrl-0 = <&pwm3_pin>;
  clocks = <&cru 351>;
  status = "disabled";
 };

 uart2: serial@ff690000 {
  compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
  reg = <0x0 0xff690000 0x0 0x100>;
  clocks = <&cru 79>, <&cru 343>;
  clock-names = "baudclk", "apb_pclk";
  interrupts = <0 57 4>;
  pinctrl-names = "default";
  pinctrl-0 = <&uart2_xfer>;
  reg-shift = <2>;
  reg-io-width = <4>;
  status = "disabled";
 };

 mbox: mbox@ff6b0000 {
  compatible = "rockchip,rk3368-mailbox";
  reg = <0x0 0xff6b0000 0x0 0x1000>;
  interrupts = <0 146 4>,
        <0 147 4>,
        <0 148 4>,
        <0 149 4>;
  clocks = <&cru 325>;
  clock-names = "pclk_mailbox";
  #mbox-cells = <1>;
  status = "disabled";
 };

 pmu: power-management@ff730000 {
  compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
  reg = <0x0 0xff730000 0x0 0x1000>;

  power: power-controller {
   compatible = "rockchip,rk3368-power-controller";
   #power-domain-cells = <1>;
   #address-cells = <1>;
   #size-cells = <0>;
# 652 "arch/arm64/boot/dts/rockchip/rk3368.dtsi"
   power-domain@12 {
    reg = <12>;
    clocks = <&cru 202>,
      <&cru 205>,
      <&cru 204>,
      <&cru 200>,
      <&cru 198>,
      <&cru 199>,
      <&cru 190>,
      <&cru 468>,
      <&cru 469>,
      <&cru 470>,
      <&cru 473>,
      <&cru 465>,
      <&cru 475>,
      <&cru 355>,
      <&cru 360>,
      <&cru 359>,
      <&cru 366>,
      <&cru 367>,
      <&cru 370>,
      <&cru 371>,
      <&cru 358>,
      <&cru 356>,
      <&cru 100>,
      <&cru 104>,
      <&cru 105>,
      <&cru 108>,
      <&cru 107>,
      <&cru 106>,
      <&cru 110>,
      <&cru 109>;
    pm_qos = <&qos_iep>,
      <&qos_isp_r0>,
      <&qos_isp_r1>,
      <&qos_isp_w0>,
      <&qos_isp_w1>,
      <&qos_vip>,
      <&qos_vop>,
      <&qos_rga_r>,
      <&qos_rga_w>;
    #power-domain-cells = <0>;
   };






   power-domain@14 {
    reg = <14>;
    clocks = <&cru 208>,
      <&cru 476>,
      <&cru 111>,
      <&cru 112>;
    pm_qos = <&qos_hevc_r>,
      <&qos_vpu_r>,
      <&qos_vpu_w>;
    #power-domain-cells = <0>;
   };





   power-domain@16 {
    reg = <16>;
    clocks = <&cru 193>,
      <&cru 192>,
      <&cru 64>;
    pm_qos = <&qos_gpu>;
    #power-domain-cells = <0>;
   };
  };
 };

 pmugrf: syscon@ff738000 {
  compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
  reg = <0x0 0xff738000 0x0 0x1000>;

  pmu_io_domains: io-domains {
   compatible = "rockchip,rk3368-pmu-io-voltage-domain";
   status = "disabled";
  };

  reboot-mode {
   compatible = "syscon-reboot-mode";
   offset = <0x200>;
   mode-normal = <(0x5242C300 + 0)>;
   mode-recovery = <(0x5242C300 + 3)>;
   mode-bootloader = <(0x5242C300 + 9)>;
   mode-loader = <(0x5242C300 + 1)>;
  };
 };

 cru: clock-controller@ff760000 {
  compatible = "rockchip,rk3368-cru";
  reg = <0x0 0xff760000 0x0 0x1000>;
  clocks = <&xin24m>;
  clock-names = "xin24m";
  rockchip,grf = <&grf>;
  #clock-cells = <1>;
  #reset-cells = <1>;
 };

 grf: syscon@ff770000 {
  compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
  reg = <0x0 0xff770000 0x0 0x1000>;

  io_domains: io-domains {
   compatible = "rockchip,rk3368-io-voltage-domain";
   status = "disabled";
  };
 };

 wdt: watchdog@ff800000 {
  compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
  reg = <0x0 0xff800000 0x0 0x100>;
  clocks = <&cru 368>;
  interrupts = <0 79 4>;
  status = "disabled";
 };

 timer0: timer@ff810000 {
  compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
  reg = <0x0 0xff810000 0x0 0x20>;
  interrupts = <0 66 4>;
  clocks = <&cru 353>, <&cru 85>;
  clock-names = "pclk", "timer";
 };

 spdif: spdif@ff880000 {
  compatible = "rockchip,rk3368-spdif";
  reg = <0x0 0xff880000 0x0 0x1000>;
  interrupts = <0 54 4>;
  clocks = <&cru 83>, <&cru 464>;
  clock-names = "mclk", "hclk";
  dmas = <&dmac_bus 3>;
  dma-names = "tx";
  pinctrl-names = "default";
  pinctrl-0 = <&spdif_tx>;
  status = "disabled";
 };

 i2s_2ch: i2s-2ch@ff890000 {
  compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
  reg = <0x0 0xff890000 0x0 0x1000>;
  interrupts = <0 40 4>;
  clock-names = "i2s_clk", "i2s_hclk";
  clocks = <&cru 84>, <&cru 462>;
  dmas = <&dmac_bus 6>, <&dmac_bus 7>;
  dma-names = "tx", "rx";
  status = "disabled";
 };

 i2s_8ch: i2s-8ch@ff898000 {
  compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
  reg = <0x0 0xff898000 0x0 0x1000>;
  interrupts = <0 53 4>;
  clock-names = "i2s_clk", "i2s_hclk";
  clocks = <&cru 82>, <&cru 463>;
  dmas = <&dmac_bus 0>, <&dmac_bus 1>;
  dma-names = "tx", "rx";
  pinctrl-names = "default";
  pinctrl-0 = <&i2s_8ch_bus>;
  status = "disabled";
 };

 iep_mmu: iommu@ff900800 {
  compatible = "rockchip,iommu";
  reg = <0x0 0xff900800 0x0 0x100>;
  interrupts = <0 17 4>;
  clocks = <&cru 202>, <&cru 468>;
  clock-names = "aclk", "iface";
  power-domains = <&power 12>;
  #iommu-cells = <0>;
  status = "disabled";
 };

 isp_mmu: iommu@ff914000 {
  compatible = "rockchip,iommu";
  reg = <0x0 0xff914000 0x0 0x100>,
        <0x0 0xff915000 0x0 0x100>;
  interrupts = <0 14 4>;
  clocks = <&cru 205>, <&cru 469>;
  clock-names = "aclk", "iface";
  #iommu-cells = <0>;
  power-domains = <&power 12>;
  rockchip,disable-mmu-reset;
  status = "disabled";
 };

 vop_mmu: iommu@ff930300 {
  compatible = "rockchip,iommu";
  reg = <0x0 0xff930300 0x0 0x100>;
  interrupts = <0 15 4>;
  clocks = <&cru 198>, <&cru 465>;
  clock-names = "aclk", "iface";
  power-domains = <&power 12>;
  #iommu-cells = <0>;
  status = "disabled";
 };

 hevc_mmu: iommu@ff9a0440 {
  compatible = "rockchip,iommu";
  reg = <0x0 0xff9a0440 0x0 0x40>,
        <0x0 0xff9a0480 0x0 0x40>;
  interrupts = <0 12 4>;
  clocks = <&cru 208>, <&cru 476>;
  clock-names = "aclk", "iface";
  #iommu-cells = <0>;
  status = "disabled";
 };

 vpu_mmu: iommu@ff9a0800 {
  compatible = "rockchip,iommu";
  reg = <0x0 0xff9a0800 0x0 0x100>;
  interrupts = <0 9 4>,
        <0 10 4>;
  clocks = <&cru 208>, <&cru 476>;
  clock-names = "aclk", "iface";
  #iommu-cells = <0>;
  status = "disabled";
 };

 qos_iep: qos@ffad0000 {
  compatible = "rockchip,rk3368-qos", "syscon";
  reg = <0x0 0xffad0000 0x0 0x20>;
 };

 qos_isp_r0: qos@ffad0080 {
  compatible = "rockchip,rk3368-qos", "syscon";
  reg = <0x0 0xffad0080 0x0 0x20>;
 };

 qos_isp_r1: qos@ffad0100 {
  compatible = "rockchip,rk3368-qos", "syscon";
  reg = <0x0 0xffad0100 0x0 0x20>;
 };

 qos_isp_w0: qos@ffad0180 {
  compatible = "rockchip,rk3368-qos", "syscon";
  reg = <0x0 0xffad0180 0x0 0x20>;
 };

 qos_isp_w1: qos@ffad0200 {
  compatible = "rockchip,rk3368-qos", "syscon";
  reg = <0x0 0xffad0200 0x0 0x20>;
 };

 qos_vip: qos@ffad0280 {
  compatible = "rockchip,rk3368-qos", "syscon";
  reg = <0x0 0xffad0280 0x0 0x20>;
 };

 qos_vop: qos@ffad0300 {
  compatible = "rockchip,rk3368-qos", "syscon";
  reg = <0x0 0xffad0300 0x0 0x20>;
 };

 qos_rga_r: qos@ffad0380 {
  compatible = "rockchip,rk3368-qos", "syscon";
  reg = <0x0 0xffad0380 0x0 0x20>;
 };

 qos_rga_w: qos@ffad0400 {
  compatible = "rockchip,rk3368-qos", "syscon";
  reg = <0x0 0xffad0400 0x0 0x20>;
 };

 qos_hevc_r: qos@ffae0000 {
  compatible = "rockchip,rk3368-qos", "syscon";
  reg = <0x0 0xffae0000 0x0 0x20>;
 };

 qos_vpu_r: qos@ffae0100 {
  compatible = "rockchip,rk3368-qos", "syscon";
  reg = <0x0 0xffae0100 0x0 0x20>;
 };

 qos_vpu_w: qos@ffae0180 {
  compatible = "rockchip,rk3368-qos", "syscon";
  reg = <0x0 0xffae0180 0x0 0x20>;
 };

 qos_gpu: qos@ffaf0000 {
  compatible = "rockchip,rk3368-qos", "syscon";
  reg = <0x0 0xffaf0000 0x0 0x20>;
 };

 efuse256: efuse@ffb00000 {
  compatible = "rockchip,rk3368-efuse";
  reg = <0x0 0xffb00000 0x0 0x20>;
  #address-cells = <1>;
  #size-cells = <1>;
  clocks = <&cru 369>;
  clock-names = "pclk_efuse";

  cpu_leakage: cpu-leakage@17 {
   reg = <0x17 0x1>;
  };
  temp_adjust: temp-adjust@1f {
   reg = <0x1f 0x1>;
  };
 };

 gic: interrupt-controller@ffb71000 {
  compatible = "arm,gic-400";
  interrupt-controller;
  #interrupt-cells = <3>;
  #address-cells = <0>;

  reg = <0x0 0xffb71000 0x0 0x1000>,
        <0x0 0xffb72000 0x0 0x2000>,
        <0x0 0xffb74000 0x0 0x2000>,
        <0x0 0xffb76000 0x0 0x2000>;
  interrupts = <1 9
        ((((1 << (8)) - 1) << 8) | 4)>;
 };

 pinctrl: pinctrl {
  compatible = "rockchip,rk3368-pinctrl";
  rockchip,grf = <&grf>;
  rockchip,pmu = <&pmugrf>;
  #address-cells = <0x2>;
  #size-cells = <0x2>;
  ranges;

  gpio0: gpio@ff750000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xff750000 0x0 0x100>;
   clocks = <&cru 320>;
   interrupts = <0 0x51 4>;

   gpio-controller;
   #gpio-cells = <0x2>;

   interrupt-controller;
   #interrupt-cells = <0x2>;
  };

  gpio1: gpio@ff780000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xff780000 0x0 0x100>;
   clocks = <&cru 321>;
   interrupts = <0 0x52 4>;

   gpio-controller;
   #gpio-cells = <0x2>;

   interrupt-controller;
   #interrupt-cells = <0x2>;
  };

  gpio2: gpio@ff790000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xff790000 0x0 0x100>;
   clocks = <&cru 322>;
   interrupts = <0 0x53 4>;

   gpio-controller;
   #gpio-cells = <0x2>;

   interrupt-controller;
   #interrupt-cells = <0x2>;
  };

  gpio3: gpio@ff7a0000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xff7a0000 0x0 0x100>;
   clocks = <&cru 323>;
   interrupts = <0 0x54 4>;

   gpio-controller;
   #gpio-cells = <0x2>;

   interrupt-controller;
   #interrupt-cells = <0x2>;
  };

  pcfg_pull_up: pcfg-pull-up {
   bias-pull-up;
  };

  pcfg_pull_down: pcfg-pull-down {
   bias-pull-down;
  };

  pcfg_pull_none: pcfg-pull-none {
   bias-disable;
  };

  pcfg_pull_none_12ma: pcfg-pull-none-12ma {
   bias-disable;
   drive-strength = <12>;
  };

  emmc {
   emmc_clk: emmc-clk {
    rockchip,pins = <2 4 2 &pcfg_pull_none>;
   };

   emmc_cmd: emmc-cmd {
    rockchip,pins = <1 26 2 &pcfg_pull_up>;
   };

   emmc_pwr: emmc-pwr {
    rockchip,pins = <1 27 2 &pcfg_pull_up>;
   };

   emmc_bus1: emmc-bus1 {
    rockchip,pins = <1 18 2 &pcfg_pull_up>;
   };

   emmc_bus4: emmc-bus4 {
    rockchip,pins = <1 18 2 &pcfg_pull_up>,
      <1 19 2 &pcfg_pull_up>,
      <1 20 2 &pcfg_pull_up>,
      <1 21 2 &pcfg_pull_up>;
   };

   emmc_bus8: emmc-bus8 {
    rockchip,pins = <1 18 2 &pcfg_pull_up>,
      <1 19 2 &pcfg_pull_up>,
      <1 20 2 &pcfg_pull_up>,
      <1 21 2 &pcfg_pull_up>,
      <1 22 2 &pcfg_pull_up>,
      <1 23 2 &pcfg_pull_up>,
      <1 24 2 &pcfg_pull_up>,
      <1 25 2 &pcfg_pull_up>;
   };
  };

  gmac {
   rgmii_pins: rgmii-pins {
    rockchip,pins = <3 22 1 &pcfg_pull_none>,
      <3 24 1 &pcfg_pull_none>,
      <3 19 1 &pcfg_pull_none>,
      <3 8 1 &pcfg_pull_none_12ma>,
      <3 9 1 &pcfg_pull_none_12ma>,
      <3 10 1 &pcfg_pull_none_12ma>,
      <3 14 1 &pcfg_pull_none_12ma>,
      <3 28 1 &pcfg_pull_none_12ma>,
      <3 13 1 &pcfg_pull_none_12ma>,
      <3 15 1 &pcfg_pull_none>,
      <3 16 1 &pcfg_pull_none>,
      <3 17 1 &pcfg_pull_none>,
      <3 18 1 &pcfg_pull_none>,
      <3 25 1 &pcfg_pull_none>,
      <3 20 1 &pcfg_pull_none>;
   };

   rmii_pins: rmii-pins {
    rockchip,pins = <3 22 1 &pcfg_pull_none>,
      <3 24 1 &pcfg_pull_none>,
      <3 19 1 &pcfg_pull_none>,
      <3 8 1 &pcfg_pull_none_12ma>,
      <3 9 1 &pcfg_pull_none_12ma>,
      <3 13 1 &pcfg_pull_none_12ma>,
      <3 15 1 &pcfg_pull_none>,
      <3 16 1 &pcfg_pull_none>,
      <3 20 1 &pcfg_pull_none>,
      <3 21 1 &pcfg_pull_none>;
   };
  };

  i2c0 {
   i2c0_xfer: i2c0-xfer {
    rockchip,pins = <0 6 1 &pcfg_pull_none>,
      <0 7 1 &pcfg_pull_none>;
   };
  };

  i2c1 {
   i2c1_xfer: i2c1-xfer {
    rockchip,pins = <2 21 1 &pcfg_pull_none>,
      <2 22 1 &pcfg_pull_none>;
   };
  };

  i2c2 {
   i2c2_xfer: i2c2-xfer {
    rockchip,pins = <0 9 2 &pcfg_pull_none>,
      <3 31 2 &pcfg_pull_none>;
   };
  };

  i2c3 {
   i2c3_xfer: i2c3-xfer {
    rockchip,pins = <1 16 1 &pcfg_pull_none>,
      <1 17 1 &pcfg_pull_none>;
   };
  };

  i2c4 {
   i2c4_xfer: i2c4-xfer {
    rockchip,pins = <3 24 2 &pcfg_pull_none>,
      <3 25 2 &pcfg_pull_none>;
   };
  };

  i2c5 {
   i2c5_xfer: i2c5-xfer {
    rockchip,pins = <3 26 2 &pcfg_pull_none>,
      <3 27 2 &pcfg_pull_none>;
   };
  };

  i2s {
   i2s_8ch_bus: i2s-8ch-bus {
    rockchip,pins = <2 12 1 &pcfg_pull_none>,
      <2 13 1 &pcfg_pull_none>,
      <2 14 1 &pcfg_pull_none>,
      <2 15 1 &pcfg_pull_none>,
      <2 16 1 &pcfg_pull_none>,
      <2 17 1 &pcfg_pull_none>,
      <2 18 1 &pcfg_pull_none>,
      <2 19 1 &pcfg_pull_none>,
      <2 20 1 &pcfg_pull_none>;
   };
  };

  pwm0 {
   pwm0_pin: pwm0-pin {
    rockchip,pins = <3 8 2 &pcfg_pull_none>;
   };
  };

  pwm1 {
   pwm1_pin: pwm1-pin {
    rockchip,pins = <0 8 2 &pcfg_pull_none>;
   };
  };

  pwm3 {
   pwm3_pin: pwm3-pin {
    rockchip,pins = <3 29 3 &pcfg_pull_none>;
   };
  };

  sdio0 {
   sdio0_bus1: sdio0-bus1 {
    rockchip,pins = <2 28 1 &pcfg_pull_up>;
   };

   sdio0_bus4: sdio0-bus4 {
    rockchip,pins = <2 28 1 &pcfg_pull_up>,
      <2 29 1 &pcfg_pull_up>,
      <2 30 1 &pcfg_pull_up>,
      <2 31 1 &pcfg_pull_up>;
   };

   sdio0_cmd: sdio0-cmd {
    rockchip,pins = <3 0 1 &pcfg_pull_up>;
   };

   sdio0_clk: sdio0-clk {
    rockchip,pins = <3 1 1 &pcfg_pull_none>;
   };

   sdio0_cd: sdio0-cd {
    rockchip,pins = <3 2 1 &pcfg_pull_up>;
   };

   sdio0_wp: sdio0-wp {
    rockchip,pins = <3 3 1 &pcfg_pull_up>;
   };

   sdio0_pwr: sdio0-pwr {
    rockchip,pins = <3 4 1 &pcfg_pull_up>;
   };

   sdio0_bkpwr: sdio0-bkpwr {
    rockchip,pins = <3 5 1 &pcfg_pull_up>;
   };

   sdio0_int: sdio0-int {
    rockchip,pins = <3 6 1 &pcfg_pull_up>;
   };
  };

  sdmmc {
   sdmmc_clk: sdmmc-clk {
    rockchip,pins = <2 9 1 &pcfg_pull_none>;
   };

   sdmmc_cmd: sdmmc-cmd {
    rockchip,pins = <2 10 1 &pcfg_pull_up>;
   };

   sdmmc_cd: sdmmc-cd {
    rockchip,pins = <2 11 1 &pcfg_pull_up>;
   };

   sdmmc_bus1: sdmmc-bus1 {
    rockchip,pins = <2 5 1 &pcfg_pull_up>;
   };

   sdmmc_bus4: sdmmc-bus4 {
    rockchip,pins = <2 5 1 &pcfg_pull_up>,
      <2 6 1 &pcfg_pull_up>,
      <2 7 1 &pcfg_pull_up>,
      <2 8 1 &pcfg_pull_up>;
   };
  };

  spdif {
   spdif_tx: spdif-tx {
    rockchip,pins = <2 23 1 &pcfg_pull_none>;
   };
  };

  spi0 {
   spi0_clk: spi0-clk {
    rockchip,pins = <1 29 2 &pcfg_pull_up>;
   };
   spi0_cs0: spi0-cs0 {
    rockchip,pins = <1 24 3 &pcfg_pull_up>;
   };
   spi0_cs1: spi0-cs1 {
    rockchip,pins = <1 25 3 &pcfg_pull_up>;
   };
   spi0_tx: spi0-tx {
    rockchip,pins = <1 23 3 &pcfg_pull_up>;
   };
   spi0_rx: spi0-rx {
    rockchip,pins = <1 22 3 &pcfg_pull_up>;
   };
  };

  spi1 {
   spi1_clk: spi1-clk {
    rockchip,pins = <1 14 2 &pcfg_pull_up>;
   };
   spi1_cs0: spi1-cs0 {
    rockchip,pins = <1 15 2 &pcfg_pull_up>;
   };
   spi1_cs1: spi1-cs1 {
    rockchip,pins = <3 28 2 &pcfg_pull_up>;
   };
   spi1_rx: spi1-rx {
    rockchip,pins = <1 16 2 &pcfg_pull_up>;
   };
   spi1_tx: spi1-tx {
    rockchip,pins = <1 17 2 &pcfg_pull_up>;
   };
  };

  spi2 {
   spi2_clk: spi2-clk {
    rockchip,pins = <0 12 2 &pcfg_pull_up>;
   };
   spi2_cs0: spi2-cs0 {
    rockchip,pins = <0 13 2 &pcfg_pull_up>;
   };
   spi2_rx: spi2-rx {
    rockchip,pins = <0 10 2 &pcfg_pull_up>;
   };
   spi2_tx: spi2-tx {
    rockchip,pins = <0 11 2 &pcfg_pull_up>;
   };
  };

  tsadc {
   otp_pin: otp-pin {
    rockchip,pins = <0 3 0 &pcfg_pull_none>;
   };

   otp_out: otp-out {
    rockchip,pins = <0 3 1 &pcfg_pull_none>;
   };
  };

  uart0 {
   uart0_xfer: uart0-xfer {
    rockchip,pins = <2 24 1 &pcfg_pull_up>,
      <2 25 1 &pcfg_pull_none>;
   };

   uart0_cts: uart0-cts {
    rockchip,pins = <2 26 1 &pcfg_pull_none>;
   };

   uart0_rts: uart0-rts {
    rockchip,pins = <2 27 1 &pcfg_pull_none>;
   };
  };

  uart1 {
   uart1_xfer: uart1-xfer {
    rockchip,pins = <0 20 3 &pcfg_pull_up>,
      <0 21 3 &pcfg_pull_none>;
   };

   uart1_cts: uart1-cts {
    rockchip,pins = <0 22 3 &pcfg_pull_none>;
   };

   uart1_rts: uart1-rts {
    rockchip,pins = <0 23 3 &pcfg_pull_none>;
   };
  };

  uart2 {
   uart2_xfer: uart2-xfer {
    rockchip,pins = <2 6 2 &pcfg_pull_up>,
      <2 5 2 &pcfg_pull_none>;
   };

  };

  uart3 {
   uart3_xfer: uart3-xfer {
    rockchip,pins = <3 29 2 &pcfg_pull_up>,
      <3 30 3 &pcfg_pull_none>;
   };

   uart3_cts: uart3-cts {
    rockchip,pins = <3 16 2 &pcfg_pull_none>;
   };

   uart3_rts: uart3-rts {
    rockchip,pins = <3 17 2 &pcfg_pull_none>;
   };
  };

  uart4 {
   uart4_xfer: uart4-xfer {
    rockchip,pins = <0 27 3 &pcfg_pull_up>,
      <0 26 3 &pcfg_pull_none>;
   };

   uart4_cts: uart4-cts {
    rockchip,pins = <0 24 3 &pcfg_pull_none>;
   };

   uart4_rts: uart4-rts {
    rockchip,pins = <0 25 3 &pcfg_pull_none>;
   };
  };
 };
};
# 8 "arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/input/input.h" 1
# 13 "./scripts/dtc/include-prefixes/dt-bindings/input/input.h"
# 1 "./scripts/dtc/include-prefixes/dt-bindings/input/linux-event-codes.h" 1
# 14 "./scripts/dtc/include-prefixes/dt-bindings/input/input.h" 2
# 9 "arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts" 2

/ {
 model = "GeekBox";
 compatible = "geekbuying,geekbox", "rockchip,rk3368";

 aliases {
  mmc0 = &emmc;
 };

 chosen {
  stdout-path = "serial2:115200n8";
 };

 memory@0 {
  device_type = "memory";
  reg = <0x0 0x0 0x0 0x80000000>;
 };

 ext_gmac: gmac-clk {
  compatible = "fixed-clock";
  clock-frequency = <125000000>;
  clock-output-names = "ext_gmac";
  #clock-cells = <0>;
 };

 ir: ir-receiver {
  compatible = "gpio-ir-receiver";
  gpios = <&gpio3 30 1>;
  pinctrl-names = "default";
  pinctrl-0 = <&ir_int>;
 };

 keys: gpio-keys {
  compatible = "gpio-keys";
  pinctrl-names = "default";
  pinctrl-0 = <&pwr_key>;

  key-power {
   gpios = <&gpio0 2 1>;
   label = "GPIO Power";
   linux,code = <116>;
   wakeup-source;
  };
 };

 leds: gpio-leds {
  compatible = "gpio-leds";

  blue_led: led-0 {
   gpios = <&gpio2 2 0>;
   label = "geekbox:blue:led";
   default-state = "on";
  };

  red_led: led-1 {
   gpios = <&gpio2 3 0>;
   label = "geekbox:red:led";
   default-state = "off";
  };
 };

 vcc_sys: vcc-sys-regulator {
  compatible = "regulator-fixed";
  regulator-name = "vcc_sys";
  regulator-min-microvolt = <5000000>;
  regulator-max-microvolt = <5000000>;
  regulator-always-on;
  regulator-boot-on;
 };
};

&emmc {
 status = "okay";
 bus-width = <8>;
 cap-mmc-highspeed;
 clock-frequency = <150000000>;
 non-removable;
 vmmc-supply = <&vcc_io>;
 vqmmc-supply = <&vcc18_flash>;
 pinctrl-names = "default";
 pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;
};

&gmac {
 status = "okay";
 phy-supply = <&vcc_lan>;
 phy-mode = "rgmii";
 clock_in_out = "input";
 assigned-clocks = <&cru 127>;
 assigned-clock-parents = <&ext_gmac>;
 pinctrl-names = "default";
 pinctrl-0 = <&rgmii_pins>;
 tx_delay = <0x30>;
 rx_delay = <0x10>;
};

&i2c0 {
 status = "okay";

 rk808: pmic@1b {
  compatible = "rockchip,rk808";
  reg = <0x1b>;
  pinctrl-names = "default";
  pinctrl-0 = <&pmic_int>, <&pmic_sleep>;
  interrupt-parent = <&gpio0>;
  interrupts = <5 8>;
  rockchip,system-power-controller;
  vcc1-supply = <&vcc_sys>;
  vcc2-supply = <&vcc_sys>;
  vcc3-supply = <&vcc_sys>;
  vcc4-supply = <&vcc_sys>;
  vcc6-supply = <&vcc_sys>;
  vcc7-supply = <&vcc_sys>;
  vcc8-supply = <&vcc_io>;
  vcc9-supply = <&vcc_sys>;
  vcc10-supply = <&vcc_sys>;
  vcc11-supply = <&vcc_sys>;
  vcc12-supply = <&vcc_io>;
  clock-output-names = "xin32k", "rk808-clkout2";
  #clock-cells = <1>;

  regulators {
   vdd_cpu: DCDC_REG1 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <700000>;
    regulator-max-microvolt = <1500000>;
    regulator-name = "vdd_cpu";
   };

   vdd_log: DCDC_REG2 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <700000>;
    regulator-max-microvolt = <1500000>;
    regulator-name = "vdd_log";
   };

   vcc_ddr: DCDC_REG3 {
    regulator-always-on;
    regulator-boot-on;
    regulator-name = "vcc_ddr";
   };

   vcc_io: DCDC_REG4 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <3300000>;
    regulator-max-microvolt = <3300000>;
    regulator-name = "vcc_io";
   };

   vcc18_flash: LDO_REG1 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <1800000>;
    regulator-name = "vcc18_flash";
   };

   vcc33_lcd: LDO_REG2 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <3300000>;
    regulator-max-microvolt = <3300000>;
    regulator-name = "vcc33_lcd";
   };

   vdd_10: LDO_REG3 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <1000000>;
    regulator-max-microvolt = <1000000>;
    regulator-name = "vdd_10";
   };

   vcca_18: LDO_REG4 {
    regulator-boot-on;
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <1800000>;
    regulator-name = "vcca_18";
   };

   vccio_sd: LDO_REG5 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <3300000>;
    regulator-name = "vccio_sd";
   };

   vdd10_lcd: LDO_REG6 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <1000000>;
    regulator-max-microvolt = <1000000>;
    regulator-name = "vdd10_lcd";
   };

   vcc_18: LDO_REG7 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <1800000>;
    regulator-name = "vcc_18";
   };

   vcc18_lcd: LDO_REG8 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <1800000>;
    regulator-name = "vcc18_lcd";
   };

   vcc_sd: SWITCH_REG1 {
    regulator-name = "vcc_sd";
   };

   vcc_lan: SWITCH_REG2 {
    regulator-always-on;
    regulator-boot-on;
    regulator-name = "vcc_lan";
   };
  };
 };
};

&pinctrl {
 ir {
  ir_int: ir-int {
   rockchip,pins = <3 30 0 &pcfg_pull_none>;
  };
 };

 keys {
  pwr_key: pwr-key {
   rockchip,pins = <0 2 0 &pcfg_pull_none>;
  };
 };

 pmic {
  pmic_sleep: pmic-sleep {
   rockchip,pins = <0 0 2 &pcfg_pull_none>;
  };

  pmic_int: pmic-int {
   rockchip,pins = <0 5 0 &pcfg_pull_up>;
  };
 };
};

&tsadc {
 status = "okay";
 rockchip,hw-tshut-mode = <0>;
 rockchip,hw-tshut-polarity = <1>;
};

&uart2 {
 status = "okay";
};

&usb_host0_ehci {
 status = "okay";
};

&usb_otg {
 status = "okay";
};

&wdt {
 status = "okay";
};